Jyi Tsong Lin

High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application

Comparison of junctionless and conventional nanowire FETs is presented. Our numerical simulation results suggest that though the junctionless device suffers low drive current due to its accumulation nature, it has an advantage in scalability. Relaxed wire diameter requirement is predicted for the junctionless case. More interestingly, it shows a great potential in ultra-low power subthreshold logic application due to superior speed, as compared with the conventional structure.

Comparative study of process variations in junctionless and conventional double-gate MOSFETs

This work presents an in-detail investigation of process variations in symmetrical junctionless double-gate CMOS using 2D numerical simulation. General variability issues including oxide thickness, gate work function, and channel thickness are discussed. Uniform probability density function was assumed for the dopant atom location in the junctionless channel. Based on the statistical doping profiles, device simulation was performed by solving 2D drift-diffusion equations with modified local density approximation as used mostly in bulks device for quantum confinement. This paper is organized as follows. Section II introduces the simulation technique for device structure. Section III presents a comprehensive analysis for impact of process fluctuations on threshold voltage. Finally, conclusions are drawn.

Subthreshold Kink Effect Revisited and Optimized for Si Nanowire MOSFETs

A device design technique for boosting nanowire MOSFET performance beyond a 10-nm technology node is proposed using physical modeling and 3-D numerical simulation. The revisited subthreshold kink effect improves the transistor ON-OFF current ratio and is achievable with supply bias lower than 1 V. The proposed technique overcomes the fundamental and thermal voltage-limited subthreshold swing (SS). An optimized device design methodology to exploit the lowered SS is provided as well.

Non-classical polycrystalline silicon thin-film transistor with embedded block-oxide for suppressing the short channel effect

In this paper, a polycrystalline silicon (polysilicon) thin-film transistor with a block oxide enclosing body, BTFT, is fabricated and investigated. By utilizing the block-oxide structure of thin-film transistors, the BTFT is shown to suppress the short channel effect. This proposed structure is formed by burying self-aligned oxide spacers along the sidewalls of the source and drain junctions, which reduces the P–N junction area, thereby reducing the junction capacitance and leakage current. Measurements demonstrate that the BTFT eliminates the punch-through effect even down to gate lengths of 1.5 µm, whereas the conventional TFT suffers serious short channel effects at this gate length.

Microscopic study of random dopant fluctuation in silicon nanowire transistors using 3D simulation

Variability impact of random dopant fluctuation in nanometer-scale silicon nanowire MOSFET is assessed via TCAD numerical simulations. We have simulated ensembles of 629 devices, which differ from each other due to the physical manifestation of the dopant variability in the channel location, including the detailed microscopic pattern of a discrete sphere dopant from drain to source. Based on our study, the variations of leakage and drive currents are not great, but not negligible. Implications from random dopant fluctuation for design are also discussed.

Threshold-voltage variability analysis and modeling for junctionless double-gate transistors

Abstract This paper presents a detailed analysis on the variation sources in junctionless double-gate transistors using numerical device simulation. Comparison with conventional ultra-scaled devices is also included in the study. When channel thickness is reduced to 10xa0nm or below, thickness variation becomes a significant source of threshold voltage variation even though random dopant fluctuation has been considered the most significant one, especially in the highly doped junctionless channel. When accounting for volume inversion in the thin silicon film, we propose a modeling approach to estimate the film thickness variation impact on threshold voltage using effective film thickness. Our study suggests that when T Si is less than 4xa0nm, the threshold voltage becomes less sensitive to film thickness variation, partly due to quantum confinement.

Investigation of discrete dopant induced variability in silicon nanowire MOSFETs using 3D simulation

Impact of discrete doping in n-type gate-all-around silicon nanowire transistors is studied using 3D numerical simulation with quantum mechanical effect accounted for. We investigate the devices in the sub-22 nm technology node based on an assumption of sphere dopants with 1 nm diameter. Comprehensive study of equal random dopant probability in the channel is first reported. Our results show that the silicon nanowire FETs have more severe threshold variation when the random dopant is located in the centre of the channel than is located near source/drain boundary. The predicted threshold voltage variability ranges from 0.19 V to 0.26 V while most cases have threshold voltages below 0.23 V. The leakage current variability is within an order of magnitude and the output current variability is within one hundred micro amperes.

Pragmatic study of the nanowire FETs with nonideal gate structures

Device characteristics of the nanowire FETs with nonideal gate structures, such as nonuniform gate oxide and elliptic wire, are investigated using 3D numerical simulation. As the nonideal nanowire cases show acceptable device characteristics and still maintain good performance projection, various nanowires FETs are thus flexible for manufacturing. By simply changing the wire diameter from 10 nm to 7 nm at the 25 nm technology node, 22% improvement in gate delay is predicted.

The Fabrication of Single Electron Transistor by Polysilicon Thin Film and Point-Contact Lithography

In this paper, point-contact lithography depended on the proximity effect is employed to fabricate the single electron transistor (SET) by using polysilicon thin film which is deposited upon an insulation layer (POI or TFT). The electrical characteristics of the SET fabricated, such as Coulomb black and Coulomb oscillation, are observed and discussed appropriately. It can be operated beyond 180 degK and the SET characteristics can be still observed. In addition, the channel width of the SET below 20 nm has been also fabricated

New concepts of SOI modelling for use in circuit simulator

In this paper some new concepts, which allow us to solve surface potentials for the two surfaces of the double gate controlled SOI device and to carry out general modelling of the device, are presented. Some simulation results from SPICE3e2 are also demonstrated.<<ETX>>