Meng Hsueh Chiang

Speed superiority of scaled double-gate CMOS

Unloaded ring-oscillator simulations, performed with a generic process/physics-based compact model for double-gate (DG) MOSFETs and supplemented with model-predicted on-state currents and gate capacitances for varying supply voltages (V/sub DD/), are used to show and explain the speed superiority of extremely scaled DG CMOS over the single-gate (e.g., bulk-Si) counterpart. The DG superiority for unloaded circuits is most substantive for low V/sub DD/ < /spl sim/1 V.

Random Dopant Fluctuation in Limited-Width FinFET Technologies

In this brief, the random-dopant-fluctuation (RDF) effects in FinFET devices are investigated via physical analyses and numerical simulations. Our results show that extremely scaled devices, particularly FinFETs with narrow device width (fin height) in each individual fin, are susceptible to RDF effects. Even in an ideally ldquoundopedrdquo silicon channel, the existence of unintended impurity dopants of acceptors and donors will still have a significant impact on device characteristics. The implication from RDF for design is also discussed.

High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations

Novel high-density low-power logic circuit techniques using DG devices

Novel high-density low-power double-gate circuit techniques for basic logic families such as NAND, NOR, and pass-gate are proposed. The technique exploits the independent front- and back-gate bias to reduce the number of transistors for implementing logic functions. The scheme substantially improves the standby and dynamic power consumptions by reducing the number of transistors and the chip area/size while improving the circuit performance. The power/performance advantages are analyzed/validated via mixed-mode two-dimensional MEDICI numerical device simulations, as well as by using physical delay equations.

Novel high-density low-power high-performance double-gate logic techniques

This paper propose novel double-gate (DG) logic circuit schemes using only symmetrical gates to reduce the area and leakage/active power. The performance improvement and power reduction for NAND, NOR, and pass-gate are studied via the two-dimensional numerical device simulator to directly simulate the circuit structures.

Temperature-based phase change memory model for pulsing scheme assessment

A physical yet analytical phase change memory (PCM) model simultaneously accounting for thermal and electrical conductivities is presented. Due to the physics based nature of the model, the essential temperature from heating and cooling of PCM during operation is instantaneously updated. More importantly, the model can be applied to non-conventional circuit design technique. We show that for the first time the input current pulsing scheme for PCM programming can be significantly simplified via the unique intrinsic thermal memory effect. The model is implemented in HSPICE using Verilog-A, which is flexible and portable for different circuit simulators. As PCM technology is emerging, the predictive compact model can expedite the novel technology development.

An Analytical Compact PCM Model Accounting for Partial Crystallization

This paper presents a simple yet predictive compact model for phase change memory (PCM). We successfully implement the model in a circuit simulator using Verilog-A. Due to the physical nature of the model, it can be used to predict the temperature and crystalline fraction in the cell, simply via SPICE simulation. This paper also demonstrates the use of the model in static resistance calculation, i.e. the set and reset statuses in R-I characteristics. More importantly, the crystal status transitions such as partial crystalline and amorphous statuses, resulting in uncertain resistance, are accounted for. The model can facilitate the PCM technology development not only in the device level, but also in the circuit level.

Operation of multi-level phase change memory using various programming techniques

In this paper, we evaluate the writing operation of multi-level phase change memory by using different programming techniques including proposed monotonically increasing and decreasing pulse, constant pulse, and slow quenching schemes. Our simulation results suggest that the proposed multi-level cell schemes not only have an advantage in density but also consume less power during writing operation.

Investigation of Temperature-Dependent Characteristics of AlGaN/GaN MOS-HEMT by Using Hydrogen Peroxide Oxidation Technique

This paper investigates the temperature-dependent performances of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT). The gate dielectric layer and surface passivation layer are formed by the H2O2 oxidation technique. The gate dielectric quality is estimated by the breakdown electric field (EBD) and low-frequency noise. The capacitance-voltage (C-V) hysteresis characteristics of MOS and Schottky diodes at 300/480 K are also studied. An appropriate thermal model is used to investigate the self-heating effect and calculate the effective channel temperature (Teff). The dc performances of the present MOS-HEMT are improved at 300/480 K, as compared with a Schottky-barrier HEMT (SB-HEMT), including output current density, maximum extrinsic transconductance (gm,max), gate voltage swing, gate-drain leakage current (IGD), specific ON-resistance (RON), three-terminal OFF-state breakdown voltage (BVOFF), and subthreshold swing. Factors that cause IGD and BVOFF are analyzed by the temperature-dependent measurement. The passivation effect of the present MOS-HEMT is also confirmed by the surface leakage measurement. The devised MOS-HEMT demonstrates superior thermal stability to the reference SB-HEMT. The present-design is promising for high-temperature electronic applications.

TiO2-dielectric AlGaN/GaN/Si metal-oxide-semiconductor high electron mobility transistors by using nonvacuum ultrasonic spray pyrolysis deposition

High-k TiO₂-dielectric Al_0.25Ga_0.75N/GaN metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) grown on Si substrates by using nonvacuum ultrasonic spray pyrolysis deposition technique are reported for the first time. The effective oxide thickness is 1.45 nm with layer thickness/dielectric constant of 20 nm/53.6. Pulse I-V and low-frequency noise spectra (1/f) are conducted to characterize the interface property. The gate leakage current I_GD is decreased by three orders at V_GD = -50 V as compared with a reference Schottky-gate device. Superior device characteristics are achieved for the present MOS-HEMT (Schottky-gate HEMT) for the gate dimensions of 1 μm × 100 μm including drain-source current density I_DS at V_GS = 0 V (I_DSS0) of 384 (342) mA/mm, maximum I_DS(I_DS, _max) of 650 (511) mA/mm, maximum extrinsic transconductance (g_m, _max) of 107 (110) mS/mm, two-terminal gate-drain breakdown voltage (BVGD) of -155 (-105) V, turn-ON voltage (VON) of 3.8 (1.8) V, ON-state breakdown (BVDS) of 139 (94) V, gate-voltage swing of 2.7 (1.7) V, and ON/OFF current ratio (I_ON/I_OFF) of 4.5 x 10⁵(3.5 x 10²).