Keunwoo Kim

Turning silicon on its edge [double gate CMOS/FinFET technology]

Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.

Random Dopant Fluctuation in Limited-Width FinFET Technologies

In this brief, the random-dopant-fluctuation (RDF) effects in FinFET devices are investigated via physical analyses and numerical simulations. Our results show that extremely scaled devices, particularly FinFETs with narrow device width (fin height) in each individual fin, are susceptible to RDF effects. Even in an ideally ldquoundopedrdquo silicon channel, the existence of unintended impurity dopants of acceptors and donors will still have a significant impact on device characteristics. The implication from RDF for design is also discussed.

High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations

Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure

An on-chip digital characterization method for local random variation in a process is presented. The method uses a sense-amplifier-based test circuit that uses digital voltage measurement instead of the analog current measurements of conventional techniques. The proposed circuit helps design fast on-chip built-in-self-test schemes for measuring random variation. A testchip is designed in 0.13mum CMOS and measured to show the effectiveness of the proposed circuit in extracting local random variation.

Novel high-density low-power logic circuit techniques using DG devices

Novel high-density low-power double-gate circuit techniques for basic logic families such as NAND, NOR, and pass-gate are proposed. The technique exploits the independent front- and back-gate bias to reduce the number of transistors for implementing logic functions. The scheme substantially improves the standby and dynamic power consumptions by reducing the number of transistors and the chip area/size while improving the circuit performance. The power/performance advantages are analyzed/validated via mixed-mode two-dimensional MEDICI numerical device simulations, as well as by using physical delay equations.

FinFET SRAM for high-performance low-power applications

The SRAM behavior of FinFET technology is investigated and compared with 90 nm node planar partially-depleted silicon-on-insulator (PD-SOI) technology. Unique FinFET circuit behavior in SRAM applications, resulting from the near-ideal device characteristics, is demonstrated by full cell cross section simulation for the first time, and shows high performance and low active and standby power. SRAM stability is analyzed in detail, as compared to PD-SOI.

Scaling planar silicon devices

The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and the elementary electronic charge. Sustained improvement in performance and density has required the introduction of new device structures and materials. Partially depleted SOI, a most recent MOSFET innovation, has extended VLSI performance while introducing unique idiosyncrasies. Fully depleted SOI is one logical extension of this device design direction. Gate dielectric tunneling, device self-heating, and single-event upsets present developers of these next-generation devices with new challenges. Strained silicon and high-permittivity gate dielectric are examples of new materials that will enable CMOS developers to continue to deliver device performance enhancements in the sub-100 nm regime.

Leakage power analysis of 25-nm double-gate CMOS devices and circuits

Leakage power and input pattern dependence of leakage for extremely scaled (L/sub eff/=25nm) double-gate (DG) circuits are analyzed, compared with those of conventional bulk-Si counterpart. Physics-based numerical two-dimensional simulation results for DG CMOS device/circuit power are presented, identifying that DG technology is an ideal candidate for low-power applications. Unique DG device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design tradeoffs for DG CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for DG device, considering state dependency, show that leakage currents for DG circuits are reduced by a factor of over 10/spl times/, compared with bulk-Si counterpart.

Extremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state current

A simulation-based analysis of extremely scaled double-gate (DG) CMOS, emphasizing the effects of gate-induced drain leakage (GIDL) in DG MOSFETs, is described. Device and ring-oscillator simulations project an enormous performance potential for DG/CMOS, but also show how and why GIDL can be much more detrimental to off-state current in DG devices than in the single-gate counterparts. However, for asymmetrical (n/sup +/ and p/sup +/ polysilicon) gates, the analysis further shows that the GIDL effect can be controlled by tailoring the back (p/sup +/-gate) oxide thickness, which implies design optimization regarding speed as well as static power in DG/CMOS circuits.

Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap

We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-kappa/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of selective device structure scaling that will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits.