K.C. Chen

Scaling evaluation of BE-SONOS NAND flash beyond 20 nm

We have successfully fabricated and characterized sub-30 nm and sub-20 nm BE-SONOS NAND flash. Good device characteristics are achieved through two innovative processes: (1) a low-energy tilt-angle STI pocket implantation to suppress the STI corner edge effect, and (2) a drain offset using an additional oxide liner to improve the short-channel effect. The conventional self-boosting program-inhibit and ISPP (incremental step pulse programming) for MLC storage are demonstrated for 20 nm BE-SONOS NAND operation. Read current stability and read disturb life time are also evaluated. The estimated number of storage electrons is only 50-100, and for the first time we have demonstrated successful data retention after 150degC baking in the ldquofew-electronrdquo regime. Our results strongly suggest that BE-SONOS is a promising charge-trapping (CT) technology for NAND Flash scaling.

Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory

Program/erase cycling stress induced read current fluctuations arising from random telegraph noise (RTN) in a localized storage, multi-level nitride flash memory (SONOS) is explored. Our study shows that localized charge storage significantly enhances RTN. The amplitude of RTN varies in different program levels of a multi-level cell. The broadening of read current distribution due to RTN is characterized and modeled. Improvement of bottom oxide robustness can reduce the read current fluctuations

Characterization and Monte Carlo Analysis of Secondary Electrons Induced Program Disturb in a Buried Diffusion Bit-line SONOS Flash Memory

A new program disturb in a buried diffusion bit-line SONOS array is observed as a bit-line width is reduced. A multi-step Monte Carlo simulation is performed to explore the disturb mechanism. We find that the Vt shift of a disturbed cell is attributed to impact ionization-generated secondary electrons in a neighboring cell when it is in programming. The effects of substrate bias, bit-line dimension and pocket implant on the program disturb are characterized and evaluated by a Monte Carlo simulation.

Highly Scalable and Reliable Multi-bit/cell Nitride Trapping Nonvolatile Memory Using Enhanced ANS-ONO Process with A Nitridized Interface

Multi-bit/cell nitride trapping NVM (Eitan et al., 2000 and 2005) using BTBT-HH erase suffers an apparent VT loss due to interface trap (NIT) generation. The array-nitride-sealing (ANS) ONO process (Shih et al., 2005) eliminates this VT loss by blocking hydrogen from the interface. In this work we further outfit the ANS-ONO process with a nitridized Si/SiO2 interface. By introducing a rapid thermal nitridation (RTN) after a low-energy buried diffusion (BD) implantation, the new process provides not only more immunity to HH-induced NIT generation but also a path to scale the BD. A 256Mb testing chip is successfully fabricated by the new approach with excellent natural good yield (>80%) and reliability. Our new process integration shows excellent reliability, scalability, and manufacturability for multi-bit/cell nitride trapping memory

A New Interference Phenomenon in Sub-60nm Nitride-Based Flash Memory

It is the first time to disclose that the similar interference from adjacent wordlines as found in floating-gate flash memory also exists in nitride-based flash memory. For sub-60nm nitride-based flash technologies, this interference effect cannot be ignored any more and should be well taken into consideration when defining the operation window of the memory products.

Program Trapped-Charge Effect on Random Telegraph-Noise Amplitude in a Planar SONOS Flash Memory Cell

Program-charge effects in a SONOS Flash cell on the amplitude of random telegraph noise (RTN) are investigated. We measure RTN in 45 planar SONOS cells and 40 floating-gate (FG) cells in erase state and program state, respectively. We find that a SONOS cell has a wide spread in RTN amplitudes after programming, while an FG cell has identical RTN amplitudes in erase and program states at the same read-current level. A 3-D atomistic simulation is performed to calculate RTN amplitudes. Our result shows that the wide spread of program-state RTN amplitudes in a SONOS cell is attributed to a current-path-percolation effect caused by random discrete nitride charges.

Polycrystalline-silicon channel trap induced transient read instability in a 3D NAND flash cell string

Vt instability caused by grain-boundary trap (GBT) in the poly-crystalline silicon (poly-Si) channel of a 3D NAND string are comprehensively studied. Experimental results reveal that trapping/detrapping of GBT would cause transient cell current with a time constant of 10us or longer, and this transient is strongly affected by the bias history. Sensing offset between program/erase verify (PV/EV) and read (RD) results in “pseudo” charge loss/gain that reduces the sensing margin. Modified EV, PV, or RD bias schemes are suggested to mitigate this effect.

Use of random telegraph signal as internal probe to study program/erase charge lateral spread in a SONOS flash memory

A novel random telegraph signal (RTS) method is proposed to study the lateral spread of injected charges in program/erase of a NOR-type SONOS flash memory. The concept is to use RTS to extract an interface trap position and to detect a local potential variation near the trap due to injection of program/erase charges. By using this method, we find that CHISEL program has a broader charge distribution than CHE program. A mismatch of CHE program electrons and band-to-band erase holes is observed directly from this method.

Program charge effect on random telegraph noise amplitude and its device structural dependence in SONOS flash memory

Nitride program charge effects on random telegraph noise (RTN) in SONOS flash cells are investigated. We measure and simulate RTN amplitudes in floating gate flash, planar SONOS, and FinFET SONOS cells. We find that a planar SONOS has a wide spread in RTN amplitude after programming while a floating gate flash cell has identical RTN amplitude in erase and program states. The spread of program-state RTN amplitudes in a planar SONOS is attributed to a current-path percolation effect caused by random discrete nitride charges. The program-state RTN spread can be significantly reduced in FinFET SONOS.

Poly-Silicon Trap Position and Pass Voltage Effects on RTN Amplitude in a Vertical NAND Flash Cell String

We investigate the dependence of random telegraph noise (RTN) on a poly-silicon trap position in a 3D vertical channel and charge-trapping NAND flash cell string. We characterize RTN in read current of each cell of a string at different read and pass voltages. RTN characteristics resulting from a trap in a read cell or in a pass cell are differentiated. A method to identify a poly-silicon trap position in a NAND string is proposed. We perform the 3D TCAD simulation to calculate channel electron density in a string. Measured RTN characteristics can be explained by current-path percolation and channel carrier screening effects. The distribution of RTN amplitudes in NAND strings is characterized.