Tahui Wang

Mechanisms of interface trap-induced drain leakage current in off-state n-MOSFET's

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFETs after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO/sub 2/ interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 /spl mu/m n-MOSFET was subjected to a dc voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsibility for the leakage current at a large drain-to-gate bias (V/sub dg/). The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression /spl Delta/I/sub d/=Aexp(B/sub it//F). The value of B/sub it/ about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V/sub dg/ decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V/sub dg/, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant. >

Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

In this paper, bottom-oxide thickness (Tbo) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with Tbo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor

Interface induced uphill diffusion of boron: an effective approach for ultrashallow junction

This paper investigates anomalous diffusion behavior for ultra low energy implants in the extension or tip of PMOS devices. Transient enhanced diffusion (TED) is minimal at these low energies, since excess interstitials are very close to the surface. Instead, interface induced uphill diffusion is found, for the first time, to dominate during low temperature thermal cycles. The interface pile-up dynamics can be taken advantage of to produce shallower junctions and improve short channel effect control in PMOS devices. Attempts to minimize TED before spacer deposition by inclusion of extra RTA anneals are shown to be detrimental to forming boron ultra shallow junctions.

Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10/sup 4/ times more efficient in trap generation than the hot electron stress in terms of injected charge.

Hot hole stress induced leakage current (SILC) transient in tunnel oxides

The mechanisms and transient characteristics of hot hole stress induced leakage current (SILC) in tunnel oxides are investigated. Positive oxide charge assisted tunneling is found to be a dominant SILC mechanism in a hot hole stressed device. The SILC transient is attributed to oxide hole detrapping and thus annihilation of positive charge assisted tunneling centers. Our characterization shows that the leakage current transient in a 100-/spl Aring/ oxide obeys a power law time dependence f/sup -n/ with the power factor n significantly less than one. An analytical model accounting for the observed time dependence is proposed.

A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs-from single electron emission to PBTI recovery transient

A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large- and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temperature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In addition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method.

Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells

The reliability issues of two-bit storage nitride flash memory cells, including low-V/sub t/ state threshold voltage instability, read-disturb, and high-V/sub t/ state charge loss are addressed. The responsible mechanisms and reliability models are discussed. Our study shows that the cell reliability is strongly dependent on operation methods and process conditions.

A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs

The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V/sub gs/ such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 /spl Aring/) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 /spl Aring/) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation.

Effects of hot carrier induced interface state generation in submicron LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 /spl mu/m LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V/sub g//spl sime/0.5 V/sub d/ in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states. >

Pocket implantation effect on drain current flicker noise in analog nMOSFET devices

The pocket implantation effect on drain current flicker noise in 0.13 /spl mu/m CMOS process based high performance analog nMOSFETs is investigated. Our result shows that pocket implantation will significantly degrade device low-frequency noise primarily because of nonuniform threshold voltage distribution along the channel. An analytical flicker noise model to account for a pocket doping effect is proposed. In our model, the local threshold voltage and the width of the pocket implant region are extracted from the measured reverse short-channel effect, and the oxide trap density is extracted from a long-channel device. Good agreement between our model and the measurement result is obtained without other fitting parameters.