K. Jaaskelainen

First test results Of MIMOSA-26, a fast CMOS sensor with integrated zero suppression and digitized output

The MIMOSA pixel sensors developed in Strasbourg have demonstrated attractive features for the detection of charged particles in high energy physics. So far, full-size sensors have been prototyped only with analog readout, which limits the output rate to about 1000 frames/second. The new MIMOSA 26 sensor provides a 2.2 cm2 sensitive surface with an improved readout speed of 10,000 frames/second and data throughput compression. It incorporates pixel output discrimination for binary readout and zero suppression micro-circuits at the sensor periphery to stream only fired pixel out. The sensor is back from foundry since february 2009 and has being characterized in laboratory and in test beam. The temporal noise is measured around 13-14 e- and an operation point corresponding to an efficiency of 99.5±0.1 % for a fake rate of 10-4 per pixel can be reached at room temperature. MIMOSA 26 equips the final version of the EUDET beam telescope and prefigures the architecture of monolithic active pixel sensors (MAPS) for coming vertex detectors (STAR, CBM and ILC experiments) which have higher requirements. Developments in the architecture and technology of the sensors are ongoing and should allow to match the desired readout speed and radiation tolerance. Finally, the integration of MAPS into a micro-vertex detector is addressed. A prototype ladder equipped, on both sides, with a row of 6 MIMOSA 26-like sensors is under study, aiming for a total material budget about 0.3% X0.

Radiation tolerance of a column parallel CMOS sensor with high resistivity epitaxial layer

CMOS Monolithic Active Pixel Sensors (MAPS) demonstrate excellent performances in the field of charged particle tracking. A single point resolution of 1–2 μm and a detection efficiency close to 100% were routinely observed with various MAPS designs featuring up to 106 pixels on active areas as large as 4 cm2[1]. Those features make MAPS an interesting technology for vertex detectors in particle and heavy ion physics. In order to adapt the sensors to the high particle fluxes expected in this application, we designed a sensor with fast column parallel readout and partially depleted active volume. The latter feature was expected to increase the tolerance of the sensors to non-ionizing radiation by one order of magnitude with respect to the standard technology. This paper discusses the novel sensor and presents the results on its radiation tolerance.

MISTRAL & ASTRAL: two CMOS Pixel Sensor architectures suited to the Inner Tracking System of the ALICE experiment

A detector, equipped with 50 μm thin CMOS Pixel Sensors (CPS), is being designed for the upgrade of the Inner Tracking System (ITS) of the ALICE experiment at LHC. Two CPS flavours, MISTRAL and ASTRAL, are being developed at IPHC aiming to meet the requirements of the ITS upgrade. The first is derived from the MIMOSA28 sensor designed for the STAR-PXL detector. The second integrates a discriminator in each pixel to improve the readout speed and power consumption. This paper will describe in details the sensor development and show some preliminary test results.

A ten thousand frames per second readout MAPS for the EUDET beam telescope

Designed and manufactured in a commercial CMOS 0.35 μm OPTO process for equipping the EUDET beam telescope, MIMOSA26 is the first reticule size pixel sensor with digital output and integrated zero suppression. It features a matrix of pixels with 576 rows and 1152 columns, covering an active area of ~224 mm. A single point resolution of about 4 μm was obtained with a pixel pitch of 18.4 μm. Its architecture allows a fast readout frequency of ~10 k frames/s. The paper describes the chip design, test and major characterisation outcome.

Intermediate Digital Monolithic Pixel Sensor for the EUDET High Resolution Beam Telescope

A high resolution beam telescope, based on CMOS Monolithic Active Pixels Sensors (MAPS), is being developed under the EUDET collaboration, a coordinated detector R&D program for a future international linear collider. A very good spatial resolution < 5 mum, a fast readout time of 100 mus for the whole array (136 times 576 pixels) and a high granularity can be obtained with this technology. A recent fast MAPS chip, designed in AMS CMOS 0.35 mum Opto process with 14 mum epitaxial layer and called MIMOSA22, was submitted to foundry. MIMOSA22 has an active area of 26.5 mm2 with a pixel pitch of 18.4 mum arranged in an array of 576 rows by 136 columns where 8 columns have analog test outputs and 128 have their outputs connected to offset compensated discriminator stages. The pixel array is divided in seventeen blocks of pixels, with different amplification gain, diode size, pixel architecture and is addressed row-wise through a serially programmable (JTAG) sequencer. Discriminators have a common adjustable threshold with internal DAC. MIMOSA22 is the last chip (IDC-Intermediate Digital Chip), before the final sensor of the EUDET-JRA1 beam telescope, which will be installed on the 6 GeV electron beam line at DESY. In this paper, laboratory test results on analog and digital parts are presented. Test beam results, obtained with a 120 GeV pion beam at CERN, are also presented. In the last part of the paper, results on irradiated chips are given.

A Digital Monolithic Active Pixel Sensor Chip in a Quadruple-Well CIS Process for Tracking Applications

A CMOS sensor chip for charged particle detection has been developed and submitted for fabrication in a 0.18 μm Quadruple-Well (N&P-Wells, Deep N&P-Wells) CMOS Image Sensor (CIS) process. Improvement of the radiation hardness, the power dissipation and the readout speed of the mainstream CMOS sensors is expected with the exploration of this process. In order to ensure better charge collection and neutron tolerance, wafers with high-resistivity epitaxial layer have been chosen. In this paper a digital CMOS sensor prototype developed in order to validate the key analog blocks (from sensing element to 1-bit digital conversion) of a binary Monolithic Active Pixel Sensor (MAPS) in this process will be presented. The digital sensor prototype comprises four different sub-arrays of 20 μm pitch 64 × 32 pixels, 128 column-level auto-zeroed discriminators, a sequencer and an output digital multiplexer. Laboratory tests results including the charge-to-voltage conversion factor, the charge collection efficiency, the temporal noise and the fixed-pattern noise are presented in details. Some irradiation results will also be given.

Design and Characterisation of a Fast Architecture Providing Zero Suppressed Digital Output Integrated in a High Resolution CMOS Pixel Sensor for the STAR Vertex Detector and the EUDET Beam Telescope

CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated their strong potential for tracking devices, particularly for flavour tagging. They are foreseen to equip several vertex detectors and beam telescopes. Most applications require high read-out speed, imposing sensors to feature digital output with integrated zero suppression. The most recent development of MAPS at IPHC and IRFU addressing this issue will be reviewed. An architecture will be presented, combining a pixel array, column-level discriminators and zero suppression circuits. Each pixel features a preamplifier and a correlated double sampling (CDS) micro-circuit reducing the temporal and fixed pattern noises. The sensor is fully programmable and can be monitored. It will equip experimental apparatus starting data taking in 2009/2010.

The Development of On-Chip Serial Link Transmitter for MAPS

Most applications of future CMOS Monolithic Active Pixel Sensors (MAPS) require high-speed digital serial data link for data transmission. Commercial monolithic serial transmitters can be found that meet the bandwidth requirements of the MAPS. However, there is no available space for additional chips on the MAPS layers in the detector. To address this issue, a serial transmitter prototype, containing a phase-locked loop (PLL) clock generator, an 8B/10B encoder, a serializer and a low-voltage differential signaling (LVDS) driver was developed. Since the clock is embedded into the data by using serial transmission, the detector material budget due to data transmission is minimized. The serial transmitter prototype is integrated in a sensor chip, MIMOSA26, developed in IPHC (Institut Pluridisciplinaire Hubert-Curien, France). It has been implemented in a 0.35 ¿m CMOS technology. This first serial transmitter prototype was designed aiming to transmit data at 160 Mbit/s. Measurements proved our design is fully functional.

A Radiation Hard Digital Monolithic Pixel Sensor for the EUDET-JRA1 Project

In the framework of the EUDET-JRA1 project (European Detector R&D towards the International Linear Collider), which consists of design, realization and implantation of a high resolution beam digital telescope, based on Monolithic Active Pixel Sensors (MAPS), an intermediate digital chip sensor, MIMOSA22, has already been delivered with good detection performances. Although this intermediate chip has fulfilled all the initial requirements of the project, it was admitted that radiation tolerance behavior of the sensor could be improved, especially if the high precision telescope is used later in a hadron testbeam infrastructure. For this purpose, a new version of the sensor, MIMOSA22-BIS, has been designed, with several improved pixel architectures, and using the same AMS 0.35 μm opto process of the sensor MIMOSA22. This paper will be focused on tests performed in laboratory conditions using a 55Fe source, and tests performed in CERN-SPS, using a 120 GeV pion beam, in order to characterize detection performances of the chip with MIPs, before and after ionizing irradiation.

On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS)

In a detector system, clock distribution to sensors must be controlled at a level allowing proper synchronisation. In order to reach theses requirements for the HFT (Heavy Flavor Tracker) upgrade at STAR (Solenoidal Tracker at RHIC), we have proposed to distribute a low frequency clock at 10 MHz which will be multiplied to 160 MHz in each sensor by a PLL. A PLL has been designed for period jitter less than 20 ps rms, low power consumption and manufactured in a 0.35 μm CMOS process.