Y. Degerli

CMOS pixel sensor development: a fast read-out architecture with integrated zero suppression

CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated their strong potential for tracking devices, particularly for flavour tagging. They are foreseen to equip several vertex detectors and beam telescopes. Most applications require high read-out speed, which imposes sensors to feature digital output with integrated zero suppression. The most recent development of MAPS at IPHC and IRFU addressing this issue will be reviewed. The design architecture, combining pixel array, column-level discriminators and zero suppression circuits, will be presented. Each pixel features a preamplifier and a correlated double sampling (CDS) micro-circuit reducing the temporal and fixed pattern noises. The sensor is fully programmable and can be monitored. It will equip experimental apparatus starting data taking in 2009/2010.

First test results Of MIMOSA-26, a fast CMOS sensor with integrated zero suppression and digitized output

The MIMOSA pixel sensors developed in Strasbourg have demonstrated attractive features for the detection of charged particles in high energy physics. So far, full-size sensors have been prototyped only with analog readout, which limits the output rate to about 1000 frames/second. The new MIMOSA 26 sensor provides a 2.2 cm2 sensitive surface with an improved readout speed of 10,000 frames/second and data throughput compression. It incorporates pixel output discrimination for binary readout and zero suppression micro-circuits at the sensor periphery to stream only fired pixel out. The sensor is back from foundry since february 2009 and has being characterized in laboratory and in test beam. The temporal noise is measured around 13-14 e- and an operation point corresponding to an efficiency of 99.5±0.1 % for a fake rate of 10-4 per pixel can be reached at room temperature. MIMOSA 26 equips the final version of the EUDET beam telescope and prefigures the architecture of monolithic active pixel sensors (MAPS) for coming vertex detectors (STAR, CBM and ILC experiments) which have higher requirements. Developments in the architecture and technology of the sensors are ongoing and should allow to match the desired readout speed and radiation tolerance. Finally, the integration of MAPS into a micro-vertex detector is addressed. A prototype ladder equipped, on both sides, with a row of 6 MIMOSA 26-like sensors is under study, aiming for a total material budget about 0.3% X0.

Performance of a Fast Binary Readout CMOS Active Pixel Sensor Chip Designed for Charged Particle Detection

We report on the performance of the MIMOSA8 (HiMAPS1) chip. The chip is a 128times32 pixels array where 24 columns have discriminated binary outputs and eight columns analog test outputs. Offset correction techniques are used extensively in this chip to overcome process related mismatches. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the Vertex Detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the eight analog outputs. Analog data, without and with a 55Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clock frequency is increased even up to 150 MHz (13.6 mus readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency. The results prove that MIMOSA8 is the first and fastest successful monolithic active pixel sensor with on-chip signal discrimination for detection of MIPs

A fast monolithic active pixel sensor with pixel-level reset noise suppression and binary outputs for charged particle detection

In order to develop precision vertex detectors for the future linear collider, fast monolithic active pixel sensors are studied. A standard CMOS 0.25 mum digital process is used to design a test chip which includes different pixel types, column-level discriminators, and a fully programmable digital sequencer. In-pixel amplification is implemented together with double sampling. Different charge-to-voltage conversion factors were obtained using amplifiers with different gains or diode sizes. Pixel architectures with dc and ac coupling to charge sensing element were proposed. Hits from conversion of 55Fe photons were recorded for the dc-coupled and ac-coupled pixel versions. Double sampling is functional and allows almost a complete cancellation of fixed pattern noise

Monolithic active pixel sensors with in-pixel double sampling operation and column-level discrimination

Monolithic Active Pixel Sensors constitute a viable alternative to Hybrid Pixel Sensors and Charge Coupled Devices for the next generation of vertex detectors. Possible application will strongly depend on a successful implementation of on-chip hit recognition and sparsification schemes. These are not a trivial task, first because of very small signal amplitudes (/spl sim/mV), originated from charge collection, which are of the same order as natural dispersions in a CMOS process, secondly because of the limitation to use only one type of transistor over the sensitive area. The paper presents a 30 /spl times/ 128 pixel prototype chip, featuring fast, column parallel signal processing. The pixel concept combines on-pixel amplification with double sampling operation. The pixel output is a differential current signal proportional to the difference between the charges collected in two consecutive time slots. The readout of the pixel is two-phase, matching signal discrimination circuitry implemented at the end of each column. The design of low-noise discriminators includes automatic compensation of offsets for individual pixels. The details of the chip design are presented. Difficulties, encountered from being the first attempt to address on-line hit recognition, are reported. Performances of the pixel and discriminator blocks, determined in separate measurements, are discussed. The essential part of the paper consists of results of first tests performed with soft X-rays from a /sup 55/Fe source.

Development of binary readout CMOS monolithic sensors for MIP tracking

Recently, CMOS monolithic active pixels sensors (MAPS) have become strong candidates for pixel detectors used in high energy physics experiments. A very good spatial resolution can be obtained with these detectors (lower than 5 microns). A recent fast MAPS chip, designed on AMS CMOS 0.35 mum Opto process and called MIMOSA16 (HiMAPS2), was submitted to foundry in June 2006. The pixel array is addressed row-wise. The chip is a 128 times 32 pixels array where 8 columns have analog test outputs and 24 have their outputs connected to offset compensated discriminator stages. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. Discriminators have a common adjustable threshold. The sequencer operates as a pattern generator which delivers control signals both to the pixels and to the column-level discriminators. This chip is the basis of the final sensor of the EUDET-JRA1 beam telescope which will be installed at DESY in 2009. In this paper, laboratory tests results using a 55Fe source together with beam tests results made at CERN using minimum ionizing particles (MIPs) are presented.

Development of Binary Readout CMOS Monolithic Sensors for MIP Tracking

Recently, CMOS Monolithic Active Pixels Sensors (MAPS) have become strong candidates for pixel detectors used in high energy physics experiments. A very good spatial resolution lower than 5 mum can be obtained with these detectors. A recent fast MAPS chip, designed in AMS CMOS 0.35 mum Opto process and called MIMOSA16 (HiMAPS2), was submitted to foundry in June 2006. The chip is a 128times32 pixels array where 8 columns have analog test outputs and 24 columns have their outputs connected to offset compensated discriminator stages. The pixel array is addressed row-wise. The array is divided in four blocks of pixels with different charge-to-voltage conversion factors and is controlled by a serially programmable sequencer. The sequencer operates as a pattern generator which delivers control signals both to the pixels and to the column-level discriminators. Discriminators have a common adjustable threshold. This chip is the basis of the final sensor of the EUDET-JRA1 beam telescope which will be installed at DESY in 2009. In this paper, laboratory tests results using a 55Fe source together with beam tests results obtained at CERN using Minimum Ionizing Particles (MIPs) are presented.

Thin, fully depleted monolithic active pixel sensor based on 3D integration of heterogeneous CMOS layers

On the way towards fast, radiation tolerant and ultra thin CMOS radiation sensors, we propose new generation of devices based on commercial availability of vertical integration of several CMOS wafers (3D Electronics). In this process, each wafer may be thinned down to about 10 microns end equipped with through-silicon vias (TSV) allowing for electrical interconnection between wafers at a very small pitch (few microns) and with a minimum material budget. The proposed prototype device is a 245×245 pixel array with a pitch of 20 μm, providing active area of 5×5 mm2. In the first silicon layer charge sensing diode and first stage buffer amplifier (source follower) are integrated, using CMOS process on high resistivity epitaxial wafers. Outputs of buffer voltage amplifiers are vertically coupled (through a poly-poly capacitor) to the following stage of processing electronics (charge integration, time continuous shaping and signal discrimination), placed in the second silicon layer (0.13 micron CMOS). The third silicon layer (also 0.13 micron CMOS) is used for implementation of digital (binary) readout with a fast, data driven, self-triggering data flow. After description of the proposed 3D device, an update of results from ongoing tests with the first CMOS MAPS prototype fabricated using high-resistivity epitaxial substrate is provided.

A ten thousand frames per second readout MAPS for the EUDET beam telescope

Designed and manufactured in a commercial CMOS 0.35 μm OPTO process for equipping the EUDET beam telescope, MIMOSA26 is the first reticule size pixel sensor with digital output and integrated zero suppression. It features a matrix of pixels with 576 rows and 1152 columns, covering an active area of ~224 mm. A single point resolution of about 4 μm was obtained with a pixel pitch of 18.4 μm. Its architecture allows a fast readout frequency of ~10 k frames/s. The paper describes the chip design, test and major characterisation outcome.

Intermediate Digital Monolithic Pixel Sensor for the EUDET High Resolution Beam Telescope

A high resolution beam telescope, based on CMOS Monolithic Active Pixels Sensors (MAPS), is being developed under the EUDET collaboration, a coordinated detector R&D program for a future international linear collider. A very good spatial resolution < 5 mum, a fast readout time of 100 mus for the whole array (136 times 576 pixels) and a high granularity can be obtained with this technology. A recent fast MAPS chip, designed in AMS CMOS 0.35 mum Opto process with 14 mum epitaxial layer and called MIMOSA22, was submitted to foundry. MIMOSA22 has an active area of 26.5 mm2 with a pixel pitch of 18.4 mum arranged in an array of 576 rows by 136 columns where 8 columns have analog test outputs and 128 have their outputs connected to offset compensated discriminator stages. The pixel array is divided in seventeen blocks of pixels, with different amplification gain, diode size, pixel architecture and is addressed row-wise through a serially programmable (JTAG) sequencer. Discriminators have a common adjustable threshold with internal DAC. MIMOSA22 is the last chip (IDC-Intermediate Digital Chip), before the final sensor of the EUDET-JRA1 beam telescope, which will be installed on the 6 GeV electron beam line at DESY. In this paper, laboratory test results on analog and digital parts are presented. Test beam results, obtained with a 120 GeV pion beam at CERN, are also presented. In the last part of the paper, results on irradiated chips are given.