K. Madhusoodanan

Geant4 simulations of semiconductor detectors (SiC) for fast neutron spectroscopy

A proton recoil method along with Silicon Carbide semiconductor detector is presented in this paper. It consist of hydrogenous converter layer to generate recoil protons by means of neutron elastic scattering (n, p) reaction and radiation hard semiconductor material (Silicon Carbide) layer to generate detectable electrical signal upon transport of recoil protons through it. Converter layer thickness is optimized for different monoenergetic and standard neutron sources using Monte Carlo based Geant4 simulation toolkit, in order to facilitate the study of detector characteristics in greater detail.

Development of pid controller algorithm over fpga for motor control in failed fuel location module in Indian fast reactors

Nuclear fuels in fast reactors are provided with a leak tight metal cladding for containment of the fission products of the nuclear reaction. Cladding tube failures are unavoidable despite careful fabrication and testing. In case of fuel clad failure, the fuel might be lost into the coolant, with potential consequences. In view of the above it is necessary that there shall be a system designed for identifying failed Fuel Sub Assembly (FSA) in the core at the earliest possible juncture immediately after detecting the presence of failed fuel. Failed fuel location module is required to find out the fuel sub assembly which has developed a wet rupture. Failure of fuel pin in central FSA is detected by indirect method and is inferred when there is no indication from any other FSA. This is done by finding out the delayed neutrons in the sample of the sodium jet coming out of from all fuel sub assemblies. This requires a sampling system, and uses a dc servomotor to select the different jets. This is done by reading from the optical encoder which senses the position of the selector valve. This system requires a smooth and accurate control of the motor to align the selector valve to the required fuel sub assembly from the initial position. Presently it is done manually, in the experimental assembly. An accurate and fast embedded system is proposed to be designed using a digital pid controller. The digital pid controller is implemented on a field programmable gate array on a parallel architecture giving us very high speeds. The simulations are performed using Xilinx 8.1 ISE and MODELSIM 6.4C tools. Communication protocol is developed with the plant wide system using RS232C protocol and local display with the help of a LCD. This paper discusses regarding the tuning of PID controller for the DC servo motor.

Investigation of Perylene as a Converter Material for Fast Neutron Detection and Spectroscopy Using GEANT4 Monte Carlo Simulations

Monte Carlo simulations have been performed to investigate the perylene (C20H12) as a converter layer for fast neutron detection and spectroscopy. Perylene is an organic semiconductor material having high hydrogen content which could be utilized as a medium of elastic scattering for fast neutrons to produce recoil protons such as in proton recoil detector. This charged recoil proton would further liberate e-hole pairs while traversing through the material which will induce the detector’s response in the associated electronics with appropriate applied reverse voltage. Perylene is used as a neutron converter layer on top of the wide band-gap semiconductor material such as silicon carbide (SiC) which can maintain its typical characteristics even in the harsh radiation environment. SiC would help in efficient charge collection resulting from recoil proton. The thickness of perylene as a converter layer was optimized and found to be ~500 μm for wide energy range of fast neutrons. This work would further aid in the comparative study of different converter material for SiC-based fast neutron detector.

A Review on HT Attacks in PLD and ASIC Designs with Potential Defence Solutions

ABSTRACT The tremendous advancement in very large scale integration technology encourages chip designers to rely on commercial electronic design automation tools, offshore fabrication services, and outsourced intellectual property cores. As third-party involvement are more in chip design cycle, integrated circuits (IC) such as programmable logic devices (PLD) and application specific ICs (ASIC) are highly vulnerable to hardware Trojan (HT) attacks. HTs are malicious additions or modifications to existing circuit elements, which can be inserted at any stages of IC life cycle to modify/destroy the functionality, reduce reliability, leak sensitive information, etc. Besides, HT can be designed either as always on or triggered only under certain operating conditions. For example, HT attacks in safety critical applications such as nuclear power plant, space and defence will jeopardise the safety and security of the unit and cause serious consequences. Hence, it is most important to ensure that the chip being in use performs only the intended function. In this paper, an in-depth analysis of feasible HT attacks in PLD and ASIC life cycles are presented. Based on the extensive literature survey on HTs and their countermeasure techniques, the state of the art HT prevention, detection, and diagnosis techniques are recommended to the valid stages of PLD and ASIC life cycles. Therefore, incorporating possible HT defence solutions in respective phases of PLD/ASIC-based safety systems thwart them against HT attacks.

Indigenous data acquisition and signal processing system for top shield thermal design validation

In Prototype Fast Breeder Reactor (PFBR), top shield consisting of roof slab, large rotatable plug, small rotatable plug and control plug. Maintaining the temperature and temperature difference across the top shield is important to limit the thermal bowing of the top shield. Thus thermal design of top shield is a complex process, which needs detailed theoretical and experimental investigation and verification. Towards this an experimental test facility, Integrated Top Shield Test Facility (ITSTF), has been conceived, constructed and commissioned. This technical note discuss about the objective of the facility and instrumentation provided for data acquisition and monitoring of the facility.

Novel approach of backplane communication for compact & field mountable I&C systems of FBR

This paper presents a novel and passive backplane communication protocol which can be used for CPU-I/O communication over backplane for I&C systems of a typical Nuclear Power Plant. This protocol is proposed as an alternate for existing protocols with essential features required for the development of reliable ultra-compact field mountable data acquisition & control systems. Customized serial communication on a non-shared bus is proposed with its benefits and limitations. Requirements for designing compact I&C systems is described with the possible approaches. The benefits achieved with this development are simple, reliable & easily verifiable interface logic on CPU/IO modules and reduced pin count backplane connector for IO modules leading to enhanced reliability. Remote Terminal Unit (RTU) design based on this developed protocol is detailed with the interface logic design, timings, electrical specifications, capabilities and connector/mechanical details. The concept validation on FPGA based hardware is also detailed.