D. Thirugnana Murthy

DSDPC: Delay signatures at different process corners based hardware trojan detection technique for FPGAs

In applications such as nuclear power plant, space and military, safety critical systems play an important role, where security is one of the crucial design parameters. Similar to software Trojans (virus), Hardware Trojans (HT) are raising security concerns in recent years. HTs are malicious additions or modifications to existing circuit elements which are implemented either as always on or triggered only under certain conditions, to disable functionality, reduce reliability and leak valuable information from the integrated chip. In this paper, we consider the scenario of HTs inserted in field programmable gate array (FPGA) devices during field operating conditions and propose a delay signature based HT detection technique. Static timing analysis is performed to measure the delay signatures of original netlist with that of netlist extracted from field configuration bit file. Since the results of electronic design automation tools are repetitive, we compare both the delay signatures and any deviation will indicate that configuration bit file/ netlist file of the original design is altered. To increase the detection efficiency, we perform static timing analysis at various process corners such as slow, typical and fast corners (at different voltage and temperature combinations) which allows us to measure the best and worst circuit delay values. Using this property, we performed simulations with Xilinx ISE tool by targeting standard benchmark circuits on Xilinx device. Experimental results reflected the difference in delay signatures if configuration bit file is tampered with in the field. The delay difference between with and without HT circuit is enhanced from slow to fast process corner, which in turn increased the HT detection efficiency.

Process Disturbance Analyzer for Nuclear Reactors

This paper details the Process Disturbance Analyzer (PDA) for 500 MWe Prototype Fast Breeder Reactor (PFBR). The various parameters that assist safe operation of the reactor are to be monitored continuously to aid post event/disturbance analysis of the plant. Some critical analog and digital signals from circuit breakers, power supply, variable speed drive etc., are fast in nature and are to be scanned at 100ms and checked for cause of the event. When an analog signal crosses a set-point, status of digital signal changes or combination of both is defined as an event. PDA is used for fast data acquisition, event detection & storage of data on event and analyzing these disturbances occurring in nuclear power plant. PDA consists of a Versa Module Europa (VME) bus based embedded system with MC68020 processor for fast data acquisition and also a display station. It stores data for 5 minutes prior to the event and for 5 minutes later to the event. PDA is required to know the initiating event and its consequences on other signals to ensure minimum downtime and hence increasing the availability of plant.

Design and Development of FPGA based VMEbus interface controller (VIC) for Computer based I&C systems of fast reactors

Versa Module Eurocard (VME) backplane bus based architecture has been standardized for Real Time Computer (RTC) based I&C systems of Indian fast reactors. A typical RTC consists of a CPU card and a set of I/O cards. VMEbus based CPU card is currently being used in the computer based I&C systems of FBTR at IGCAR. The CPU card uses a commercial VMEbus Interface controller (VIC), which is now obsolete, to perform the functions of VMEbus system controller, VMEbus master and Interrupt Handler. To solve the part obsolescence problem and support long term maintainability, it has been envisaged to prototype VIC in a Field Programmable Gate Array (FPGA). The specifications of the commercial VIC have been revised to suit the application, retaining only the features essential for the target application. This paper discusses the design, development, verification and testing of customized VIC.

A Review on HT Attacks in PLD and ASIC Designs with Potential Defence Solutions

ABSTRACT The tremendous advancement in very large scale integration technology encourages chip designers to rely on commercial electronic design automation tools, offshore fabrication services, and outsourced intellectual property cores. As third-party involvement are more in chip design cycle, integrated circuits (IC) such as programmable logic devices (PLD) and application specific ICs (ASIC) are highly vulnerable to hardware Trojan (HT) attacks. HTs are malicious additions or modifications to existing circuit elements, which can be inserted at any stages of IC life cycle to modify/destroy the functionality, reduce reliability, leak sensitive information, etc. Besides, HT can be designed either as always on or triggered only under certain operating conditions. For example, HT attacks in safety critical applications such as nuclear power plant, space and defence will jeopardise the safety and security of the unit and cause serious consequences. Hence, it is most important to ensure that the chip being in use performs only the intended function. In this paper, an in-depth analysis of feasible HT attacks in PLD and ASIC life cycles are presented. Based on the extensive literature survey on HTs and their countermeasure techniques, the state of the art HT prevention, detection, and diagnosis techniques are recommended to the valid stages of PLD and ASIC life cycles. Therefore, incorporating possible HT defence solutions in respective phases of PLD/ASIC-based safety systems thwart them against HT attacks.

Embedded system design for I&C of Prototype Fast Breeder Reactor

High dependability on Instrumentation and control (I & C) systems calls utmost importance for smooth functioning as well as the safety of Nuclear power plants. I&C systems are employed for monitoring of the parameters, control of these parameters and protection of the plant and persons. The Embedded systems play major role in design and development of I&C systems. While designing I&C systems of Prototype Fast Breeder Reactors (PFBR), they are categorized into safety critical, safety related and non nuclear safety systems. Since embedded systems are used in safety systems, the hardware and software quality are of paramount importance which ensures safety and availability of the plant. The issues in designing safety systems which calls for high dependability with features like simple, failsafe, high availability to be deployed in mission critical applications. The challenges and issues in employing the embedded systems for PFBR I&C are elaborated in this paper. It discusses the standards and guidelines available for mission critical application and their suitability in adopting the latest technology. This paper also briefs the requirements, architecture, design & development methodology and qualifications of I&C systems of PFBR. The illustrations of the embedded systems designed and developed for PFBR I&C as case study are presented in this paper.