K. N. Bhat

Fermi level depinning at the germanium Schottky interface through sulfur passivation

We demonstrate the depinning of Fermi level on both p- and n-type germanium after sulfur passivation by aqueous (NH4)(2)S treatment. Schottky contacts realized using metals with a wide range of work functions produce nearly ideal behavior confirming that the Fermi level is depinned. Examination of the passivated surface using x-ray photoelectron spectroscopy reveals bonding between Ge and sulfur.It is shown that good Ohmic contacts to n-type Ge and a hole barrier height (phi(Bp)) of 0.6 eV to p-type Ge can be achieved after this passivation treatment, with Zr Schottky contacts. This is the highest phi(Bp) reported so far.

A CMOS Gas Sensor Array Platform With Fourier Transform Based Impedance Spectroscopy

A CMOS gas sensor array platform with digital read-out containing 27 sensor pixels and a reference pixel is presented. A signal conditioning circuit at each pixel includes digitally programmable gain stages for sensor signal amplification followed by a second order continuous time delta sigma modulator for digitization. Each sensor pixel can be functionalized with a distinct sensing material that facilitates transduction based on impedance change. Impedance spectrum (up to 10 KHz) of the sensor is obtained off-chip by computing the fast Fourier transform of sensor and reference pixel outputs. The reference pixel also compensates for the phase shift introduced by the signal processing circuits. The chip also contains a temperature sensor with digital readout for ambient temperature measurement. A sensor pixel is functionalized with polycarbazole conducting polymer for sensing volatile organic gases and measurement results are presented. The chip is fabricated in a 0.35 μm CMOS technology and requires a single step post processing for functionalization. It consumes 57 mW from a 3.3 V supply.

An early in-situ stress signature of the AlN-Si pre-growth interface for successful integration of nitrides with (111) Si

The integration of Metal Organic Chemical Vapor Deposition (MOCVD) grown group III-A nitride device stacks on Si (111) substrates is critically dependent on the quality of the first AlN buffer layer grown. A Si surface that is both oxide-free and smooth is a primary requirement for nucleating such layers. A single parameter, the AlN layer growth stress, is shown to be an early (within 50 nm), clear ( 1 GPa), and fail-safe indicator of the pre-growth surface, and the AlN quality required for successful epitaxy. Grain coalescence model for stress generation is used to correlate growth stress, the AlN-Si interface, and crystal quality.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (I¦ c) saturates to I¦ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute I¦ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.

Design, Development, Fabrication, Packaging, and Testing of MEMS Pressure Sensors for Aerospace Applications

In this chapter we present the design, fabrication, packaging, and calibration of silicon micro machined piezo-resistive pressure sensors for operation in the pressure range of 1.2–400 bar. Based on the detailed Finite Element Analysis (FEA), the diaphragm dimensions and the optimized locations for the piezo-resistors are designed, to achieve the best performance parameters over a wide range of pressures, with minimum nonlinearity and adequate burst pressure. The process parameters are optimized and the pressure sensors fabricated in the Centre for Nano Science and Engineering (CeNSE) at IISc. The wafers are diced, the devices mounted on headers, wire bonded and packaged suitably, tested, and calibrated at the cell level to determine the adequacy of the performance parameters of the sensors for different pressure ranges. The results achieved on the pressure transducer assembly with Active Temperature Compensation and the offset compensation using electronics and EMI filters in a single package are presented. Excellent linearity within 0.5 % in the output voltage versus pressure is demonstrated, over the specified pressure ranges (i) 0−1.2 bar and (ii) 0−400 bar, and over the temperature range of −40°C to +80°C.

Silicon surface texturing with a combination of potassium hydroxide and tetra-methyl ammonium hydroxide etching

A two step silicon surface texturing, consisting of potassium hydroxide (KOH) etching followed by tetra-methyl ammonium hydroxide etching is presented. This combined texturing results in 13.8% reflectivity at 600 nm compared to 16.1% reflectivity for KOH etching due to the modification of microstructure of etched pyramids. This combined etching also results in significantly lower flat-band voltage (VFB) (−0.19 V compared to −1.3 V) and interface trap density (Dit) (2.13 × 1012 cm−2 eV−1 compared to 3.2 × 1012 cm−2 eV−1).

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) = 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T)

Trap assisted avalanche instability and safe operating area concerns in AlGaN/GaN HEMTs

This work reports the very first systematic study on the physics of avalanche instability and SOA concerns in AlGaN/GaN HEMT using sub-μs pulse characterization, post stress degradation analysis, well calibrated TCAD simulations and failure analysis by SEM and TEM. Impact of electrical, as well as thermal effects on SOA boundary and avalanche instability are investigated. Trap assisted cumulative nature of degradation is studied in detail, which was discovered to be the root cause for avalanche instability in AlGaN/GaN HEMTs. Post failure SEM/TEM analysis reveal distinct failure modes in presence and absence of carrier trapping.

Self assembled monolayers of Octadecyltrichlorosilane for dielectric materials

Treatment of surfaces to change the interaction of fluids with them is a critical step in constructing useful microfluidics devices, especially those used in biological applications. Selective modification of inorganic materials such as Si, SiO2 and Si3N4 is of great interest in research and technology. We evaluated the chemical formation of OTS self-assembled monolayers on silicon substrates with different dielectric materials. Our investigations were focused on surface modification of formerly used common dielectric materials SiO2, Si3N4 and a-poly. The improvement of wetting behaviour and quality of monolayer films were characterized using Atomic force microscope, Scanning electron microscope, Contact angle goniometer, Raman spectroscopy and X-ray photoelectron spectroscopy (XPS) monolayer deposited oxide surface.

Impact of carrier quantum confinement on the short channel effects of double-gate silicon-on-insulator FINFETs

In this work, we use a center potential based approach to determine the electrostatics viz. threshold voltage (Vth), Sub-Threshold Slope and Drain Induced Barrier Lowering (DIBL) for Fully Depleted (FD) Undoped Symmetric Double-Gate (DG) Silicon-on-Insulator (SOI) FINFETs over a wide range of Channel Lengths (Lg) and drain voltages (Vd). Based on this approach, a comparison of the electrostatics of Undoped Symmetric Double-Gate (DG) Silicon-on-Insulator (SOI) FINFETs is presented between the semi-classical and quantum confinement cases for two different SOI fin thicknesses of Tfin=2nm and Tfin=7nm, respectively. For both cases, it is observed that the threshold voltage roll-off and DIBL is greater in the quantum confinement case than in the semi-classical case. This seemingly counter-intuitive trend also implies that the channel length corresponding to the transition from long channel to short channel behavior (Lmin) is also lower in the semi-classical case compared to the quantum confinement case. This behavior is explained by comparing the Lateral Electric field (along the channel length) with the Electric Field along the thickness of the SOI fin for Tfin=2nm and Tfin=7nm over a wide range of gate and drain voltages. This analysis suggests that quantum confinement adversely affects the short channel effects and leads to an increase in the Lmin compared to the semi-classical case. These results for Lmin clearly illustrate the importance of the need to include the quantum confinement effects while evaluating the electrostatics performance and scalability of symmetric DG SOI FINFETs.