A. Pouydebasque

Advances, challenges and opportunities in 3D CMOS sequential integration

3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications.

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced

Advances in 3D CMOS sequential integration

For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 4Å of the Equivalent Oxide Thickness is measured when a low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization.

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

We present in this letter the most aggressive dimensions reported to date in Ge-channel transistors: pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm). By improving both the Ge-enrichment technique and the transistor fabrication process, we demonstrate devices with controlled threshold voltage (Vth) and excellent short-channel effects. Moreover, the low defectivity and the very low thickness of the Ge film lead to a record drain OFF-state leakage for Ge-channel devices (< 1 nA/¿m at VDS = -1 V) and thus, to the best ON-state to OFF-state current ratio (ION/IOFF ~5 × 105), even at Lg = 55 nm.

Setting up 3D sequential integration for back-illuminated CMOS image sensors with highly miniaturized pixels with low temperature fully depleted SOI transistors

This paper presents an innovative 3D architecture capable of overcoming pixel miniaturization drawbacks. Back-illuminated photodiodes are realized on a first silicon layer, while readout transistors are located on a second silicon layer. Implications of a sequential integration are evaluated in the perspective of low noise pixel performances with a comprehensive study on: 1/ setting the thermal budget limit to 700degC to preserve transfer gate performances, 2/ transferring high quality SOI by direct bonding 3/ processing HfO2/TiN fully depleted transistors, exhibiting noise levels close to standard 2.2 mum pixels, with improvement solutions.

3D monolithic integration

3D monolithic integration, thanks to its high vertical density of interconnections, is the only available option for applications requiring connections at the transistor scale. However to achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low thermal budget top FET still have to be solved. In this work, a 3D monolithic process flow relying on molecular wafer bonding is proposed and results in all critical steps are given. Significant breakthroughs have been obtained using a full wafer molecular bonding with thin interlayer dielectric and an original salicidation process stabilized up to 650°C enabling to reach high performance for the top and bottom transistor. With such technology, we demonstrate functional top and bottom transistors as well as 3D structures such as invertors and SRAMs.

Localized ultra-thin GeOI: An innovative approach to germanium channel MOSFETs on bulk Si substrates

In this paper we compare two innovative approaches to the integration of Ge-channel on Insulator MOSFETs from conventional Bulk-Si substrates. The first one is based on the Ge-condensation process, and the second one relies on the epitaxy of a pure ultra-thin 2.3 nm-thick Ge layer performed directly on Si. With the second approach, we demonstrate for the first time highly-performant Localized GeOI pMOS devices down to 75 nm gate length, with controlled threshold voltage and drive current up to 600 muA/m@-1.1 V. We show a +35% improvement in drive current compared to Si references for the same Gate overdrive.

Enabling 3D Monolithic Integration

P. Batude, M. Vinet, L. Clavelier, A. Pouydebasque, C. Tabone, A. Roman, L. Baud, V. Carron, F. Nemouchi, L. Sanchez, and S. Deleonibus. CEA-LETI, Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. perrine.batude@cea.fr 3D integration is regularly mentioned for its potential in decreasing interconnection delay, and for the density gain brought by stacking several transistors layers. An additional benefit of 3D integration lies in an independent optimization of n-FET and p-FET allowed by stacking entire p-FET onto n-FET layers. In this integration scheme, connecting the layers at the transistor scale is absolutely mandatory. 3D monolithic integration, with its high alignment performance fulfils this requirement whereas parallel integration falls short in this aspect (best alignment performance at 1 sigma ~0.5μm). To achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low TB (Thermal Budget) top FET still have to be solved. In this paper, a 3D monolithic process flow relying on molecular Wafer Bonding (WB) (fig.1) is proposed and breakthroughs in the critical steps are presented. It allows full enhancement of n and p-FET performance through material choice, strain options, surface and channel orientation and metal workfunction tuning. Note that WB, contrary to other techniques for upper thin film realisation based on recristallisation, offers the possibility to co-integrate different surface and channel orientations. Furthermore this mature process step leads to a high quality crystalline top film with low TB. For the top crystalline layer realization, a Ge or Si on insulator substrate is bonded at room temperature on the fully processed bottom transistor layer after planarization of its topology (fig.1(b)). A low temperature anneal (200°C) is performed to strengthen the bonding interface before mechanical substrate removal. The bonding is found of excellent quality with bonding energy of 900 mJm (mazzara method) and clean acoustic and infrared characterisation as shown in figure 2 (a,b) . Note that the Inter Layer Dielectric (ILD) thickness (fig.2(c)) is thinned down to 100 nm and allows dense 3D contacts. Indeed this additional depth, specific to 3D technology must be minimized to enable the contact scalability as its etching and filling become critical. To spare the bottom FET from high temperature anneal for top transistor dopant activation, which would have detrimental impact on its performance, SPE (Solid Phase Epitaxial) on thin SOI films (<30nm) has been investigated. Ge pre-amorphization was performed prior to boron implantation followed by a 600°C, 2min anneal. Fig.4 displays the sheet resistance Rs junction depth Xj trade-off dopants thanks to SPE. Excellent results are obtained that are in line with the most advanced annealing obtained for p-techniques (SPE, Laser, Flash) [2,3] on bulk and clearly outperform conventional RTP results. Furthermore HfO2 integration as gate dielectrics leads to an overall budget limited to 600°C. However at this temperature, the classical NiSi agglomerates, leading to a strongly increased sheet resistance and possible encroachement. To stabilise the silicide, an original treatment based on platinum incorporation associated with fluorine and tungsten implantation is proposed. Fig.5 clearly highlights the benefits of this NiSi treatment which ensure its stability at 650°C. In addition, bi-layer contact realisation can be performed with a single lithography step as shown in fig.6. Finally, equal lithography alignment performance for top and bottom layers have been obtained (tab.1), this implies that no additional enclosure is needed for contact design rules leading to high vertical connection density. As a conclusion, we have demonstrated the technological breakthroughs (low temperature WB with thin ILD, low temperature dopant activation using SPE and stabilisation of silicide) that enable to process high performance transistors on top and bottom layer without any detrimental impact of top transistor realisation thus settling the main drawback in 3D monolithic processing. Acknowledgements This work was supported by the French National Research Agency (ANR) through Carnot funding. References [1] Topol et al, IEDM 2005 / [2] Pouydebasque et al, ESSDERC 2005 / [3] Sugoro et al, IWJT 2004/ [4] Strane et al, VLSI TSA 2007

20nm gate length trigate pFETs on strained SGOI for high performance CMOS

We present the shortest and narrowest high-κ/metal gate n- and pFETs on compressively strained enriched SiGe On Insulator (c-SGOI) reported to date (L<inf>G</inf>=20nm; W=30nm; T<inf>SiGe</inf>=15nm). The range of active area widths in this work allows observing the transition from biaxial to uniaxial stress due to lateral elastic strain relaxation, and its benefit down to 20nm gate length on hole mobility and pFET performance (up to ×2.85 I<inf>Dlin</inf> enhancement vs. SOI, I<inf>ON</inf>=520µA/µm / I<inf>OFF</inf>=130nA/µm at L<inf>G</inf>=20nm and V<inf>DS</inf>=−1V). Moreover, an improved electrostatic integrity compared to SOI pFETs is demonstrated in c-SGOI (DIBL=120mV/V vs. 160mV/V, respectively at L<inf>G</inf>=30nm). Combined to the intrinsic |V<inf>th,p</inf>| lowering properties of c-SiGe, these characteristics qualify trigate c-SGOI as a very promising candidate for high performance pMOSFETs.

Refinement of the Subthreshold Slope Modeling for Advanced Bulk CMOS Devices

We present here a simple analytical model of the subthreshold slope of CMOS devices that successfully describes the long-channel plateau, the initial improvement for medium gate lengths, and the final degradation for short gate lengths. The model is based on the voltage-doping transformation (VDT) that leads to a new term in the subthreshold slope expression, explaining the degradation of the slope at very short channels. The potential minimum at the virtual cathode was expressed using a semiempirical expression that allows our model to fit to data that were extracted from simulation in a wide range of device parameters. Finally, the new slope model successfully reproduced experimental data that were measured on devices based on 90- and 65-nm technologies, demonstrating the validity of our model for advanced bulk CMOS technologies.