B. Duriez

Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping

We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at VDS=-0.5 V, good short-channel effect control, and high transconductance (gm=1.2 mS/μm at VDS=-1 V and 1.05 mS/μm at VDS=-0.5 V for LG=70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.

Demonstration of scaled Ge p-channel FinFETs integrated on Si

We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1]. Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 0.5V), good SCE control and high transconductance (1.2 mS/μm at 1V, 1.05 mS/μm at 0.5V) are achieved. The Ge FinFET presented in this work exhibits highest gm/SS at Vdd=1V reported for non-planar unstrained Ge pFETs to date.

An Ultralow-Resistance Ultrashallow Metallic Source/Drain Contact Scheme for III–V NMOS

We report an ultrashallow metallic source/drain (S/D) contact scheme for fully self-aligned III-V NMOS with specific contact resistivity and sheet resistance which, for the first time, demonstrate performance metrics that may be compatible with the ITRS R_ext requirements for 12-nm technology generation device pitch. The record specific contact resistivity between the contact pad and metallic S/D of ρ_c = 2.7 ·10^-9 Ω·cm² has been demonstrated for 10 nm undoped InAs channels by forming an ultrashallow crystalline ternary NiInAs phase with R_sh = 97 Ω/sq for a junction depth of 7 nm. The junction depth of the S/D scheme is highly controllable and atomically abrupt.

Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers

We demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs integrated onto 300mm Si wafers for which the best device shows record peak g_{m, ext}=2.7mS/μm (g_{m, int}=3.3mS/μm), Q (≡g_{m, ext}/SS_sat) = 32.4 and I_on= 497μA/μm at I_off = 100nA/μm, all at V_ds= -0.5V. The high performance is a result of successful integration of <;110> oriented, highly scaled Ge fins on silicon substrates and of a low D_it gate stack with capacitance equivalent thickness=8Å. This optimized gate stack supports the highest hole mobility ever reported at sub-10Å CET. Furthermore, Ge FinFETs in the present work outperform any other reported Ge devices by more than ~2.5× (g_m/SS metric) and ~2× (I_on/I_off metric) at shortest gate lengths (down to 20nm) to the best of our knowledge.

First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

Vt-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, beta-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in beta-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.

Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs

This study combines direct measurements of channel strain, electrical mobility measurements and a rigorous modeling approach to provide insight about the strain induced mobility enhancement in FinFETs and guidelines for the device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel technique. A large vertical compressive strain is observed in FinFETs and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFETs lateral interfaces w.r.t. (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of the fin-width, fin-height and fin-length stress components on n- and p-FinFETs mobility and to identify optimal stress configurations.

Ge n-channel FinFET with optimized gate stack and contacts

Whilst high performance p-channel Ge MOSFETs have been demonstrated [1-4], Ge n-channel MOSFET drive current has been lagging behind mainly hampered by high access resistance and poor gate stack passivation [5-9]. In this work, we address these issues on a module level and demonstrate Ge enhancement mode nMOS FinFETs fabricated on 300mm Si wafers implementing optimized gate stack (D_it <; 2×10¹¹ eV^-1·cm^-2), n+-doping (Nd > 1×10²⁰ cm^-3) and metallization (ρ_c = 1×10^-7 Ωcm²) modules. L_G ~ 40 nm devices achieved I_on = 50 μA/μm at I_off = 100 nA/um, S ~ 124 mV/dec, at V_DD = 0.5V. The same gate stack and contacts were deployed on planar devices for reference. Both FinFET and planar devices in this work achieved the highest reported g_m/S_sat at 0.5 V to date for Ge nMOS enhancement mode transistors to the best of our knowledge at shortest gate lengths.

Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

This paper presents for the first time a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration. Through the optimization of the Si<inf>45</inf>Ge<inf>55</inf>/Si cap deposition and the workfunction metal, high performance devices with balanced V<inf>t,sat</inf> (+0.12V, −0.16V) at scaled T<inf>inv</inf>∼1nm and gate length L<inf>g</inf>∼30nm are reported, leading to 17ps ring oscillators at 1µW/stage at Vdd=0.7V. Compatibility with gate last processing is also demonstrated.

Atomistic modeling of impurity ion implantation in ultra-thin-body Si devices

Source/drain formation in ultra-thin body devices by conventional ion implantation is analyzed using atomistic simulation. Dopant retention is dramatically reduced by backscattering for low-energy and low-tilt angles, and by transmission for high angles. For the first time, molecular dynamics and kinetic Monte Carlo simulations, encompassing the entire Si body, are applied in order to predict damage during implant and subsequent recovery during anneal. These show that amorphization should be avoided as recrystallization in ultra-thin-body Si leads to twin boundary defects and poly-crystalline Si formation, despite the presence of a mono-crystalline Si seed. Rapid dissolution of end-of range defects in thin-body Si, caused by surface proximity, does not significantly reduce diffusion lengths. The conclusions of the atomistic modeling are verified by a novel characterization methodology and electrical analysis.

InAs N-MOSFETs with record performance of I on = 600 μA/μm at I off = 100 nA/μm (V d = 0.5 V)

Record setting III-V MOSFETs are reported. For the first time performance better than state-of-the-art HEMTs is demonstrated. For a MOSFET with 10 nm unstrained InAs surface channel and L_g = 130 nm operating at 0.5 V, on-current as high as I_on = 601 μA/μm (at fixed I_off = 100 nA/μm) is achieved. This record performance is enabled by g_{m, ext} = 2.72 mS/μm and S = 85 mV/dec, DIBL = 40 mV/V, resulting from breakthroughs in epitaxy and III-V/dielectric interface engineering. Measured mobility is 7100 cm²/V.s at n_s = 6.7×10¹² cm^-2. Device simulations further elucidate the performance potential of III-V N-MOSFETs.