K. Romanjek

Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible Tunnel FET performance

We report for the first time experimental investigations on SOI, Si1-xGexOI & GeOI Tunnel FET (TFET). These devices were fabricated using a Fully Depleted SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower IOFF (~30fA/mum) compared to co-processed CMOS. We successfully solve the TFET bipolar parasitic conduction by a novel TFET architecture, the Drift Tunnel FET (DTFET), with improved OFF state control. Concerning the ON current issue, we improve the SOI p (resp. n) TFET ION by a factor 55 (resp. 8) by source-drain profiles optimization (via spacers & extensions). Moreover, we demonstrate for the first time functional TFET & CMOS devices on Si1-xGexOI (x=15-30-100%) co-integrated with the same SOI process flow, enabling TFET ION continuous improvement with Ge content increase: ION x2700 for GeOI (compared to SOI).

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced

Automatic Extraction Methodology for Accurate Measurements of Effective Channel Length on 65-nm MOSFET Technology and Below

The length of MOSFET channels is an important circuit design parameter, and this paper focuses on a new industrially-compatible technique using gate-to-channel measurements Cgc(Vg) to provide accurate extraction of the channel length. Thanks to fully-automatic probers, the technique provides large scale extractions and so, statistical-based results can be extracted with a maximized reliability. An in-depth study of parasitic capacitances has been performed to improve the extraction accuracy to within a few nanometers.

Challenges and Progress in Germanium-on-Insulator Materials and Device Development towards ULSI Integration

SOITEC, Parc Technologique des Fontaines, F38190, Bernin, France The recent progress in the fabrication of GeOI substrates and devices is reviewed. Improvements have been made in threading dislocation density, Ge-buried oxide interface passivation, device performance. The potential of various co-integration schemes (lateral and vertical) has been illustrated as alternatives to the fabrication of n-type germanium channel devices. GeOI is also shown to be a versatile platform for the monolithic integration of Si and III-V devices and tunneling field effect transistors.

Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity

We report here experimental investigations on GeOI pMOSFET: Besides the +65% mobility enhancement in narrow channel GeOI pMOSFETs as compared to wide channels, attributed to improved sidewall transport properties, 〈100〉 channel orientation transport is investigated for the first time in Ge (001): unlike Si, no current gain is observed compared to 〈110〉 channel orientation. Finally, ballisticity rates (BR) and source injection velocities (vinj) were extracted, demonstrating 22% higher vinj in Ge than in Si.

High performance 70nm gate length Germanium-On-Insulator pMOSFET with high- /metal gate

We demonstrate for the first time 70 nm gate length TiN/HfO₂ pMOSFETs on 200 mm GeOI wafers, with excellent performances: I_ON=330 muA/mum & I_OFF=1 muA/mum @ V_d=-1.2 V (without germanide). These performances are obtained using adapted counterdoping and pocket implants. We report the best CV/I vs. I_OFF trade-off for Ge or GeOI: CV/I=4.4 ps, I_OFF=500 nA/mum @ V_d=-1 V. Moreover, based on fine electrical characterizations (mu, D_it, R_access) at T=77-300 K, in-depth analysis of both ON & OFF states were carried out. Besides, calibrated TCAD simulations were performed to predict the performance enhancements which can be theoretically reached after further device optimization. By using germanide and reducing both interface state density and diode leakage we expect I_ON=450 muA/mum, IOFF=100 nA/mum @ V_d=-1 V for L_g=70 nm.

Experimental Evidence of Sidewall Enhanced Transport Properties of Mesa-Isolated (001) Germanium-On-Insulator pMOSFETs

In this brief, the hole transport properties of narrow-width germanium-on-insulator (GeOI) pMOSFETs are investigated. We report, for the first time, +65% low-field hole mobility enhancement in narrow-width (0.29-mum effective width<i>W</i> _eff) versus large-width (10- mum <i>W</i> _eff) GeOI mesa-isolated devices. The observed enhancement, which is independent of the device length down to 90 nm, is attributed to improved sidewall transport properties resulting in higher hole mobility on the sides than on the top of the devices. At high inversion charge density <i>N</i> _inv~ 10¹³ cm^-2, + 55% hole effective mobility improvement is preserved. The top and side low-field mobilities ( mu_top and mu_side, respectively) were extracted, showing + 90% mobility improvement at the sides (mu_top = 125 cm²/V middots^-1 and mu_side= 240 cm²/V middots^-1).

High-k/metal Gate GeOI pMOSFET: Validation of the Lim&Fossum model for interface trap density extraction

The extraction of the trap density on Ge/gate-stack (top) and Ge/BOX (bottom) interfaces of germanium-on-insulator pMOSFETs is shown using the Lim & Fossum model historically developed for fully depleted SOI devices. The doping and the thickness of the Ge film do not change significantly the top interface trap density. The bottom one is slightly raised by doping the Ge film. This method can be used as a simple and efficient meaning of the interface trap density levels monitoring during process optimization of GeOI devices.

First Demonstration of Deep Sub-Micron Germanium-on-Insulator PMOSFET with Adapted Threshold Voltage

Germanium MOSFET is considered as a promising alternative to silicon due to its intrinsically higher carrier mobility, especially for holes. Using appropriate channel and pocket implants, this paper presents for the first time well-behaved short channel devices characteristics featuring a negative Vth and no parasitic conduction at the BOx interface. After a brief presentation of the device fabrication, sub-threshold characteristics are discussed. The linear drain off-current can be reduced by a factor of 200 with channel+pocket implants. The effect of the drain voltage Vj is reflected in a strong band to band tunneling (BTBT) in the off-state leakage that can be reduced by junction optimization.

Improved extraction of GIDL in FDSOI devices for proper junction quality analysis

In this work, an optimized method to extract GIDL parameters has been used to characterize junction quality in FDSOI devices. This paper gives a practical methodology to properly apply this method: first, it insists on the importance to discriminate the respective contributions of GIDL and gate tunneling in drain current. Then, an activation energy criterion is used to determine the bias conditions that are appropriate to correct application of this method. Experimental values of “tunneling” field and tunneling parameter are extracted, with better reliability than with previous methods. Reliable extractions of the GIDL parameters enable to characterize junction quality independently of junction abruptness and of the impact of traps in the bandgap. This method is successfully applied and results are in agreement with expected results.