S. Soliveres

High-

For the first time, we report high-kappa/metal-gate pMOSFETs fabricated on high-quality 200-mm germanium-on-insulator (GeOI) wafers obtained by the Ge enrichment technique. The highest mobility peak (200 cm2/V.s) and driving current (ION= 115 muA/ mum at VG - Vth = -0.8 V and VDS = -1.2 V, for L = 0.5 mum) have been demonstrated for GeOI HfO2/TiN pMOSFETs on Ge layers as thin as 50 nm. As compared to silicon-on-insulator control devices, 2times enhancement of peak mobility has been achieved. Due to temperature variation experiments and technology computer-aided design simulations, we have investigated the key physical phenomena responsible for the measured OFF currents (band-to-band tunneling at high VDS and generation-recombination via the Shockley-Read-Hall process at low VDS).

\kappa

We demonstrate for the first time 70 nm gate length TiN/HfO₂ pMOSFETs on 200 mm GeOI wafers, with excellent performances: I_ON=330 muA/mum & I_OFF=1 muA/mum @ V_d=-1.2 V (without germanide). These performances are obtained using adapted counterdoping and pocket implants. We report the best CV/I vs. I_OFF trade-off for Ge or GeOI: CV/I=4.4 ps, I_OFF=500 nA/mum @ V_d=-1 V. Moreover, based on fine electrical characterizations (mu, D_it, R_access) at T=77-300 K, in-depth analysis of both ON & OFF states were carried out. Besides, calibrated TCAD simulations were performed to predict the performance enhancements which can be theoretically reached after further device optimization. By using germanide and reducing both interface state density and diode leakage we expect I_ON=450 muA/mum, IOFF=100 nA/mum @ V_d=-1 V for L_g=70 nm.

and Metal-Gate pMOSFETs on GeOI Obtained by Ge Enrichment: Analysis of ON and OFF Performances

Germanium MOSFET is considered as a promising alternative to silicon due to its intrinsically higher carrier mobility, especially for holes. Using appropriate channel and pocket implants, this paper presents for the first time well-behaved short channel devices characteristics featuring a negative Vth and no parasitic conduction at the BOx interface. After a brief presentation of the device fabrication, sub-threshold characteristics are discussed. The linear drain off-current can be reduced by a factor of 200 with channel+pocket implants. The effect of the drain voltage Vj is reflected in a strong band to band tunneling (BTBT) in the off-state leakage that can be reduced by junction optimization.

High performance 70nm gate length Germanium-On-Insulator pMOSFET with high- /metal gate

Transport in double-gate (DG) transistors offers unusual properties due to the coupling between the two channels. We report on room-temperature negative transconductance in germanium-on-insulator DG transistors in the subthreshold regime. The effect is due to the coupling between conducting channels, analogous to the velocity modulation transistor (VMT). Unlike the VMT, our effect can be induced by either of the gates and arises not from a difference in the channel mobilities but from partial electric field screening at low channel densities combined with the density dependence of mobility. The negative transconductance becomes weaker as gate length LG is reduced.

First Demonstration of Deep Sub-Micron Germanium-on-Insulator PMOSFET with Adapted Threshold Voltage

This paper presents an experimental analysis of the noise measurements performed in germanium on insulator (GeOI) 0.12 μm PMOS transistors. The front gate stack is composed of a SiO2/HfO2 material with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front gate and back gate oxides/Ge interfaces are characterized. The slow oxide trap densities of the two interfaces are extracted. The values obtained for the front gate oxide are N<inf>t</inf>(E<inf>Fn</inf>) = 1.2 10¹⁸ cm⁻³ eV⁻¹ and are comparable to values for nitrided oxides on Si bulk. The extracted values for slow oxide trap densities of the SiO<inf>2</inf>/Ge interface are between 6 and 8 1017 cm⁻³ eV⁻¹ and are close to those of state of art buried oxide SiO<inf>2</inf>/Si interfaces. These results are of importance for the future development of GeOI technologies.

Negative transconductance in double-gate germanium-on-insulator field effect transistors

This paper presents an experimental analysis of the noise measurements performed in germanium on insulator (GeOI) 0.12 μm PMOS transistors. The front gate stack is composed of a SiO2/HfO2 material with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The slow oxide trap density of the front gate oxide is Nt(EFn) = 1.2 1018 cm−3 eV−1 and is comparable to values for nitrided oxides on Si bulk. These results are of importance for the future development of GeOI technologies.

Interface oxide trap characterisation in germanium-on-insulator 0.12 μm PMOS transistors by drain current noise measurements

This contribution presents a low frequency noise characterization of germanium (Ge) semi‐conducting bars, directly relating to the quality of the Ge film in GeOI transistors. We propose an experimental method to dissociate the intrinsic noise of the semi‐conducting bar from the access region noise by using 4 point probe (Kelvin) structures. An accurate value of Hooge’s parameter for the studied Ge technology is extracted. We obtain α of 2.6 10−4 which is an indication of the good quality of the studied Ge semiconductor material.