K. S. R. Krishna Prasad

Power optimized PLL implementation in 180nm CMOS technology

This paper describes the design of power optimized phase locked loop for frequency synthesis, Clock and Data recovery, carrier synchronization and many more communication and VLSI applications. PLL consist of Phase Frequency Detector, charge pump along with passive low pass filter and wide tuning VCO. A modified ring oscillator with tuning range of 280 MHz to 2.47GHz and phase noise of -112.4dBc/Hz at 1MHz offset is designed. Frequency Detector consist of DFF along with CMOS gates with low power architectures. Traditional charge pump, passive low pass filter, modified ring oscillator and divider for frequency synthesis offers less power and system noise. PLL proposed here has lock in range from 500MHz to 1GHz with output frequency ranging from 1GHz to 2GHz, maximum pull in time of 244ns and maximum power consumed is 252μW at 2GHz.

Medical image compression using advanced coding technique

Modern medical imaging requires storage of large quantities of digitized clinical data. Due to the constrained bandwidth and storage capacity, however, a medical image must be compressed before transmission and storage. Among the existing compression schemes, Integer based discrete cosine transform coding is one of the most effective strategies. Image data in spatial domain is transformed into spectral domain after transformation to attain higher compression gains. Based on the quantization strategy, coefficients of low amplitude in the transformed domain are discarded using a threshold technique: set partitioning in hierarchical trees (SPIHT) where in only significant coefficients are retained to increase the compression ratio without inducing salient distortion. In this paper, we used two advanced coding engines context adaptive variable length coding (CAVLC) and embedded block coding with optimal truncation (EBCOT) to code the significant coefficients. Recording or transmitting the significant coefficients instead of the whole coefficients achieves the goal of compression.. Simulations are carried out on different medical images, which include CT skull, angiogram and MR images. Consequent images demonstrate the performance of two coding engines in terms of PSNR & bpp without perceptible alterations. Simulation results showed that the Integer DCT with SPIHT and CAVLC coding has shown better results compared to JPEG & JPEG2000 schemes. Therefore, our proposed method is found to preserve information fidelity while reducing the amount of data.

ON chip LDO voltage regulator with improved transient response in 180nm

An ON chip LDO voltage regulator is presented in this paper with improved transient response. The sluggish nature of pass transistor mandates techniques to improve transient ripple and settling time against sudden load transients. An independent fast path is employed that facilitates the LDO to respond quickly to the sudden load variations. This enables reduction in the consequent ripple in the output voltage. The fast path is designed in such a way that it provides easy migration to the other process without much degradation in the performance. The proposed LDO is designed to provide a constant voltage of 1.2V and is implemented in UMC 1.8 mu CMOS technology. It features peak overshoot as low as 60 mV and very fast settling time of 6 musec.

High accuracy LDO regulator with fast transient response

This paper presents a modified single Miller capacitor feed forward compensation design for regulators resulting in a linear LDO (low dropout) regulator whose performance is independent of the off-chip capacitor and its ESR (equivalent series resistor). The proposed compensation method ensures the stability of the feedback loop and the sufficient phase margin of the LDO regulator. The proposed design is implemented using cadence 0.18 mu technology. The circuit is operable down to input voltages of 2 V with a zero-load quiescent current flow of 60 uA. The novelty here is that the capacitor less concept is introduced with SMFFC topology and also an extra feed forward stage improved the stability to a greater extent.

A Robust Low-Voltage On-Chip LDO Voltage Regulator in 180 nm

This paper proposes a capacitor-less LDO with improved steady-state response and reduced transient overshoots and undershoots. The novelty in this approach is that the regulation is improved to a greater extent by the improved error amplifier in addition to improved transient response against five vital process corners. Also entire quiescent current required is kept below 100  𝜇 A . This LDO voltage regulator provides a constant 1.2 V output voltage against all load currents from zero to 50 mA with a maximum voltage drop of 200 mV. It is designed and tested using Spectre, targeted to be fabricated on UMC 180 nm.

A Low Power, Frequency-to-Digital Converter CMOS Based Temperature Sensor in 65 nm Process

A low power all CMOS based smart temperature sensor is introduced without using any bandgap reference or any current/voltage analog-to-digital converter. With the intention of low cost, power and area consumption, the proposed temperature sensor operates in sub-threshold region generating a temperature dependent frequency from the proportional to absolute temperature current. A digital output is obtained from the temperature dependent frequency by using a 12-bit asynchronous counter. A temperature insensitive ring oscillator is designed used a reference clock signal in counter. The temperature sensor is implemented using 65 nm CMOS standard process and its operation is validated through post-layout simulation results, at a power supply of (0.5–1)-V. The sensor has an uncalibrated accuracy of +2.4/–2.1 °C for (–55 to 125) °C and a resolution of 0.28 °C for the same range. The power and area consumed by the sensor is 1.55 µW and 0.024 mm2 respectively.

An efficient low voltage buck regulator in 180nm

A current sensing circuit which is fully integrated suitable for low voltage buck regulator is presented. The current sensing circuit presented operates with accuracy close to 100 percent. It is targeted to be fabricated with 180 nm UMC technology. This IC senses faithfully till frequencies 2 MHz and hence it works well for the buck converters whose switching frequencies are up to 2 MHz. It is designed to operate with a biasing current of 100 ¿A. The designed circuit is tested with a 1.8 V buck converter and is found to sense the inductor current with an absolute error less than 1 percent against the Li-ion battery voltage variation of 2.8 to 4.8 V and a load current variation from 50 mA to 200 mA. The corresponding ripple is kept well below 20 mV.

An Adaptively Biased Capacitor-Less Low Dropout Regulator with Improved Transient Performance

A novel fully on-chip low dropout (LDO) linear regulator with a supply voltage of 1.6V, dropout voltage of 200mV and a quiescent current of 64.4μA is presented in this paper. The slew rate limitations of conventional low dropout regulator (LDR) employing folded cascode structure are overcome by fixed bias LDR (FB LDR) with the usage of recycled transistors of conventional LDR. The FB LDR with its limited input common mode range limits the transient response. The adaptive bias LDR (AB LDR) overcomes these limitations of FB LDR and further enhances the transient performance. However, fast rise and fall time demands of advanced digital technology demand the regulator to respond to corresponding fast load changes. These challenges are addressed by an additional fast reacting path. An undershoot of 89.95mV for a load current changes from 0mA to 100mA and an overshoot of 150.1mV for a current change of 100–0mA is observed for the adaptive bias transient enhanced LDR. The load regulation of 20.6μV/mA and power supply rejection (PSR) of −47.8dB@ 10kHz is achieved due to the improved closed loop gain and bandwidth of LDR. The standard 180nm UMC CMOS process is employed.

250mA ultra low drop out regulator with high slew rate double recycling folded cascode error amplifier

This paper presents a modified folded cascode error amplifier of low dropout (LDO) regulator and a compensation scheme to improve the transient response. The proposed error amplifier enhances its transconductance, gain, and slew rate by recycling the shunt current sources of conventional folded cascode amplifier without increasing area or power consumption. The design is implemented in a standard UMC 0.18μm CMOS process. The LDO regulator consumes a quiescent current of 34μAonly. Simulation results show that the overshoot/undershoot in the output voltage under the extreme load transients are 177.7mV/139mVfor load current range of 0.5mA to 250mA with an output capacitor of 1pF. The LDO presented is useful for chip level power management suitable for SoC applications.

A low phase noise 10-G bits/s clock and data recovery circuit with modified D latch for backplane applications using dual loop architecture

In this paper a clock and data recovery circuit (CDR) with modified D latch is designed meeting the standards of 10 Base-KR standard backplane. The designed circuit employs dual loop architecture in 0.18μm UMC CMOS technology. The simulated results indicate a phase noise of voltage controlled oscillator (VCO) as -173.782dBC/HZ, VCO gain of 350MHz/V while consuming 85mW from 1.8V supply. LC oscillator is designed for achieving low jitter.