Sreehari Rao Patri

A Robust Low-Voltage On-Chip LDO Voltage Regulator in 180 nm

This paper proposes a capacitor-less LDO with improved steady-state response and reduced transient overshoots and undershoots. The novelty in this approach is that the regulation is improved to a greater extent by the improved error amplifier in addition to improved transient response against five vital process corners. Also entire quiescent current required is kept below 100  𝜇 A . This LDO voltage regulator provides a constant 1.2 V output voltage against all load currents from zero to 50 mA with a maximum voltage drop of 200 mV. It is designed and tested using Spectre, targeted to be fabricated on UMC 180 nm.

A Low Power, Frequency-to-Digital Converter CMOS Based Temperature Sensor in 65 nm Process

A low power all CMOS based smart temperature sensor is introduced without using any bandgap reference or any current/voltage analog-to-digital converter. With the intention of low cost, power and area consumption, the proposed temperature sensor operates in sub-threshold region generating a temperature dependent frequency from the proportional to absolute temperature current. A digital output is obtained from the temperature dependent frequency by using a 12-bit asynchronous counter. A temperature insensitive ring oscillator is designed used a reference clock signal in counter. The temperature sensor is implemented using 65 nm CMOS standard process and its operation is validated through post-layout simulation results, at a power supply of (0.5–1)-V. The sensor has an uncalibrated accuracy of +2.4/–2.1 °C for (–55 to 125) °C and a resolution of 0.28 °C for the same range. The power and area consumed by the sensor is 1.55 µW and 0.024 mm2 respectively.

MATLAB/SIMULINK based time-domain behavioral modeling of multibit sigma-delta converters

The paper presents an approach for design of sigma-delta (ΣΔ) converters. This technique helps in finding the appropriate architecture and topology of ΣΔ modulator along with block level specifications. The design approach is implemented on the MATLAB/SIMULINK platform, that involves statistical and simulation based optimization techniques at different block levels. A 16-bit, 250 KHz signal bandwidth discrete-time switched capacitor ΣΔ converter is implemented using this technique. The behavioral model developed resulted in an ENOB of 15.58 bits, SNR of 105.9dB and third order distortion of -117.563dB. The technique besides saving time, provides more resilience in the design and simulations of ΣΔ modulators.

Fully On chip area efficient LDO voltage regulator

A novel full on-chip, area efficient low dropout linear regulator is presented in this paper. This LDO is designed with a recycling folded cascode error amplifier that offers very good stability and a load regulation of 6.760μV/mA. A refined frequency compensation scheme is used which maintains LDO stability over entire load current range i.e. 0-100mA and fast transient response without any necessity of output capacitor. The overshoot/undershoot in the output voltage under the extreme load transients are 195.3mV /71.7mV. The area of the presented LDO is greatly reduced due to removal of on-chip high output capacitance. The area of presented LDO is only 0.05 mm2. The LDO presented requires a bias current of 70μA and 200mV dropout voltage and is designed in 180nm technology.

An enhanced grey wolf optimization algorithm with improved exploration ability for analog circuit design automation

A novel circuit sizing technique with improved accuracy and efficiency is proposed to resolve the sizing issues in the analog circuit design. The grey wolf optimization (GWO) algorithm has the total number of iterations divided equally for exploration and exploitation, overlooking the impact of balance between these two phases, aimed for the convergence at a globally optimal solution. An enhanced version of a typical GWO algorithm termed as enhanced grey wolf optimization (EGWO) algorithm is presented with improved exploration ability and is successfully applied in analog circuit design. A set of 23 classical benchmark functions is evaluated and the outcomes are compared with recent state of the art. A conventional two-stage CMOS operational amplifier circuit realized in UMC 180nm CMOS technology is used as a benchmark to validate the efficiency and accuracy of the proposed optimization technique. A statistical study is also conducted over the final solution to investigate the exploration ability of the algorithm proving it to be one of the robust and reliable techniques.

An Adaptively Biased Capacitor-Less Low Dropout Regulator with Improved Transient Performance

A novel fully on-chip low dropout (LDO) linear regulator with a supply voltage of 1.6V, dropout voltage of 200mV and a quiescent current of 64.4μA is presented in this paper. The slew rate limitations of conventional low dropout regulator (LDR) employing folded cascode structure are overcome by fixed bias LDR (FB LDR) with the usage of recycled transistors of conventional LDR. The FB LDR with its limited input common mode range limits the transient response. The adaptive bias LDR (AB LDR) overcomes these limitations of FB LDR and further enhances the transient performance. However, fast rise and fall time demands of advanced digital technology demand the regulator to respond to corresponding fast load changes. These challenges are addressed by an additional fast reacting path. An undershoot of 89.95mV for a load current changes from 0mA to 100mA and an overshoot of 150.1mV for a current change of 100–0mA is observed for the adaptive bias transient enhanced LDR. The load regulation of 20.6μV/mA and power supply rejection (PSR) of −47.8dB@ 10kHz is achieved due to the improved closed loop gain and bandwidth of LDR. The standard 180nm UMC CMOS process is employed.

A low power, high accuracy amperometric potentiostat for NO x gas sensors

A low power, 1-V and an area efficient CMOS amperometric potentiostat is designed for gas sensors exploiting the benefits of room temperature ionic liquids. A regulated cascode current mirror is used as current replicating interface, which results in better performance in terms of gain, input/output resistance, bandwidth and linearity. The potentiostat is implemented in 65 nm CMOS standard process, resulting in detection of redox current of 0.2 nA–12.3 μA and having a power consumption of 11.5 μW, while having an area of 0.018 mm2.

On-chip CMOS temperature sensor with current calibrated accuracy of −1.1°C to +1.4°C (3σ) from −20°C to 150°C

This paper proposes a new sensor circuit to monitor on-chip frequency temperature changes in VLSI circuits. The proposed circuit exploits the temperature dependency of current/voltage of metal-oxide-semiconductor field effect transistor. The variation of current/voltage in the temperature sensor circuit with respect to temperature is subjected to a ring oscillator which provides the relative frequency translation. The circuit is implemented in 0.18μm CMOS technology for a temperature range of -20°C to +150 °C, operates with two point calibration, having an uncertainty of -1.1°C to +1.4°C, consumes a low energy of 0.31nJ per sample and a power consumption of 0.093μW at 12MHz frequency. A switch is used at reference clock frequency to perform self-calibration, hence removing the effects of mismatch and process variation.

High speed self biased current sense amplifier for low power CMOS SRAM's

Sense amplifiers are one of the important circuits in the CMOS memories as they have a greater impact on the access time and power dissipation of memory cells. The current-mode sense amplifiers have improved the access time as well as power dissipation to a large extent when compared to voltage-mode sense amplifiers, thus resulting in making the memories compatible with the high speed CMOS technologies. In this paper, a new topology of current-mode sense amplifiers is introduced which overcomes the imperfections associated with the conveyer based current-mode sense amplifiers. The circuit has resulted in a low sense delay of 596.6 psecs and power dissipation of 0.87uW and in the end the effect of bit-line capacitances on sense delay, power supply and temperature on power dissipation is calculated.

An output capacitor-less cascode flipped voltage follower based low dropout regulator

In this paper, a multi feedback loop, output capacitor-less LDO is proposed. The proposed LDO uses an adaptively biased folded cascode error amplifier and cascode flipped voltage follower (FVF) at the output. The LDO is designed in UMC 180nm technology, with an input voltage of 1.8V and a regulated output voltage of 1.6V. The LDO achieves a load regulation to an accuracy of 0.059V/A; the undershoot and overshoot of 100mV and 76mV, respectively for a load current step of 0 - 100mA, with rise/fall time of 500ns, within a settling time of 730ns. Contrary to Miller frequency compensation, indirect frequency compensation with split transistors is used. A total compensation capacitance of 6.7pF is used to achieve stability. The LDO consumes a total quiescent current of 61uA.