K. Sri Rama Krishna

ANN models for coplanar strip line analysis and synthesis

Neural networks recently gained attention as fast and flexible vehicles to microwave modeling, simulation and optimization. After learning and abstracting from microwave data, through a process called training, neural network models are used during microwave design to provide instant answers to the task learned. This paper presents simple and accurate ANN models for the analysis and synthesis of CPS structures to very accurately compute the characteristic parameters and the physical dimensions respectively for the required design specifications.

Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing

Tunnel FETs (TFETs) as steep slope devices have attracted much attention for designing energy efficient digital systems at scaled supply voltages. In this paper, we propose a circuit/architectural co-design approach for designing reliable and energy efficient adder cells for new computing platforms at supply voltages as low as 0.1V. At circuit level, widely used XOR gates such as 6T and 8T designs are explored and at the architectural level, adder cells with static CMOS like design (28T), tarnsmission gate design (24T), XOR based design (22T and 18T), and MUX based design (MBFA-22T) have been considered. The performance of all TFET designs have been benchmarked with 20nm double gate Si Fin FET technology. TFET designs have lower energy and energy delay product (EDP) due to TFETs steep sub threshold slope characteristics at 0.1V. 18T design is more energy efficient with slight trade-off in logic swing (i.e., robustness) and 22T and 28T designs are more robust and optimal energy efficient options.

Improved emotion recognition using GMM-UBMs

In recent past a lot of scientific attention is paid on recognizing the emotional state of the speaker from his speech. Emotion recognition is a challenging task as human emotions are complex, subtle and emotive state in human speech does not persist long. So it is important to study the presence of emotion identifiable information in smaller segments of speech. This study is aimed at studying the presence of emotional specific information with relevance to the position of the word in the utterance. During the present study, spectral features are employed to represent emotion specific information in speech. Spectral features from smaller speech segments of speech based on their position in the utterance are employed to study the presence of emotion in speech. Due to the lack of adequate data in small speech segments to support conventional GMM during the course of present study Gaussian mixture modeling with a universal background model (GMM-UBM) is used for developing a emotion recognition system. Speech data from IITKGP-SESC is used during the course of the present study. During the present study 4 (Anger, Fear, Happy and Neutral) emotions are considered.

Combining SIFT and Invariant Color Histogram in HSV space for Deformation and viewpoint Invariant Image Retrieval

This paper presents a novel approach to retrieve images which are taken at different viewpoints, using combined feature descriptors. The content of the image is extracted with two descriptors, Scale Invariant Feature Transform (SIFT) and Deformation and view point Invariant Color Histogram (ICH) in HSV color space. SIFT has been proven to be the most reliable descriptor for rotation, translation and partially to illumination and affine or 3D projection invariant image matching. However, it is designed for gray images. Invariant Histogram is developed for creating color Histogram based on color gradients which are invariant to deformation and changes in viewpoint and is developed in RGB color space. To increase the deformation and viewpoint invariance capability and thus to improve image recognition, SIFT features are combined with ICH in HSV color space for Image Retrieval. Experimental results show that robust retrieval can be achieved even for seriously occluded images.

Wavelet Based Saliency Detection for Stereoscopic Images Aided by Disparity Information

In the field of Computer vision, dependable assessment of visual saliency permits suitable processing of pictures deprived of earlier learning of their substance, and therefore sustains as an imperative stride in numerous errands including segmentation, object identification, and Compression. In this paper, we present a novel saliency recognition model for 3D pictures in view of highlight difference from luminance, color, surface texture, and depth. Difference of the stereo pair is extricated utilizing sliding window strategy. Then we present a contrast based saliency identification method that assesses global contrast divergences and spatial lucidness at the same time. This calculation is straightforward, proficient, and produces full determination saliency maps by combination of the considerable number of elements removed. Our calculation reliably performed better than existing saliency discovery strategies, yielding higher accuracy. We likewise show how the extricated saliency guide can be utilized to make top notch division covers for ensuing picture handling.

Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET’s steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has ∼91% smaller energy delay product (EDP) and ∼84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2V VDD.

Nano-scale Transistors with Circuit Interaction for Designing Energy-Efficient and Reliable Adder Cells at Low VDD

ABSTRACT Designing reliable and energy-efficient circuits with CMOS technology scaling is a pressing challenge at scaled supply voltages. This paper provides design insights and circuit interaction approach with two such emerging devices, double-gate FinFETs and tunnel field effect transistors (TFETs), for designing basic computing building blocks such as adder cells. At the circuit level, TFET-based transmission gate logic 1-bit full adder (TGLA) and improved transmission gate logic 1-bit full adder (ITGLA) cells have been proposed and designed taking into unidirectional conduction and ambipolar currents of TFETs into consideration. The performance of TFET designs has been benchmarked with 20 nm double-gate Si FinFET technology. ITGLA design is a better energy-efficient option in comparison to TGLA design with FinFETs but has reduced reliability. It has been demonstrated that the steep slope characteristics of TFETs enable both TGLA and ITGLA designs to display improved energy efficiency and reliability characteristics (in the form of reduced overshoot, reduced glitches, improved logic swing, etc.). These characteristics make TFETs desirable candidates for reliable and energy-efficient computing architectures at scaled supply voltages.

Performance benchmarking of tunnel transistors for energy efficient 4-bit adder architectures at low V DD

Tunnel field-effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. This paper presents design analysis and benchmarking of TFET based three different 1-bit full adders (8T-XOR Logic, 6T-XOR Logic and MUX Based) are used for designing 4-bit adders in two different topologies targeting a VDD below 500 mV. These topologies are 22T/18T 1-bit full adder based 4-bit carry propagate adder (22T/18TCPA) and multiplexer logic 1-bit full adder based 4-bit carry propagate adder (MCPA). The performance of TFET based 4-bit adder topologies has been benchmarked with 20 nm double gate Si FinFET technology. Tunnel FETs are desirable candidates for building energy efficient and reliable arithmetic blocks with supply voltage scaling. We demonstrate that TFETs steep slope characteristics enable the 22TCPA design to be energy efficient option along with improved reliability and 18TCPA design is the best in terms of energy efficiency and reliability amongst all designs at low supply voltages.

Detection of Bundle Branch Block Using Bat Algorithm and Levenberg Marquardt Neural Network

Abnormal Cardiac beat identification is a key process in the detection of heart ailments. This work proposes a technique for the detection of Bundle Branch Block (BBB) using Bat Algorithm (BA) technique in combination with Levenberg Marquardt Neural Network (LMNN) classifier. BBB is developed when there is a block along the electrical impulses travel to make heart to beat. The Bat algorithm can be effectively used to find changes in the ECG by identifying best features (optimized features). For the detection of normal and Bundle block beats, these Bat feature values are given as the input for the LMNN classifier.

Modeling of double ridge waveguide using ANN

The ridge waveguide is useful in various microwave applications because it can be operated at a lower frequency and has lower impedance and a wider mode separation than a simple rectangular waveguide. An accurate model is essential for the analysis and design of ridge waveguide that can be obtained using electromagnetic simulations. However, the electromagnetic simulation is expensive for its high computational cost. Therefore, artificial neural networks (ANNs) become very useful especially when several model evaluations are required during design and optimization. Recently, ANNs have been used for solving a wide variety of radio frequency (RF) and microwave computer-aided design (CAD) problems. Analysis and design of a double ridge waveguide has been presented in this paper using ANN forward and inverse models. For the analysis, a simple ANN forward model is used where the inputs are geometrical parameters and the outputs are electrical parameters. For the design of RF and microwave components, an inverse model is used where the inputs are electrical parameters and the outputs are geometrical parameters. This paper also presents a comparison of the direct inverse model and the proposed inverse model.