Ramesh Vaddi

Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction

Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS technologies for digital, analogue and RF designs. However, it has been demonstrated by several researchers that TFET circuits face increased on-state Miller capacitance effect, which leads to poor transient characteristics with large overshoots and undershoots. This would minimise the reliability of TFET circuits though energy efficient. This work gives more design insights (optimal sizing, number of stages, supply voltage) into TFET circuit reliability and proposes a TFET based circuit interaction design approach for ultra-low power and reliable ring oscillator circuit design. It has been shown that TFET circuit designs without proper reliability enhancement techniques such as circuit interaction or co-design approach exhibits very large undershoots/overshoots (∼20–50%). The proposed TFET circuit co-design approach (i.e. differential topology based design in comparison with the complementary static TFET logic designs) enhances the TFET circuit reliability by minimising the undershoots/overshoots to less than 0.5% with a trade-off in operating frequency and power consumption.

Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics

Spin Transfer Torque Magnetic Random Access memory (STT-MRAM) is found to be one of the best candidates among all emerging non-volatile memories. High write energy is a bottleneck for CMOS based 1T and 2T STT-MRAM cells with scaling. To reduce the write energy of an STT-MRAM cell, a novel 2T Hybrid (Hetero-junction and Homo-junction) Tunnel Field Effect Transistor (TFET) based STT-MRAM cell has been proposed in this paper. The proposed 2T Hybrid TFET based STT-MRAM cell has less write energy and switching time due to TFET’s combined steep-slope and ambipolar characteristics in comparison to 1T/2T-FinFET, 1T/2T Hetero-junction TFET, 1T/2T homo-junction TFET based STT-MRAM cells.

Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs

Energy efficient buffer circuits enable high speed and reliable information transfer among sub-systems of System on Chip (SoC). A novel buffer circuit design exploiting the steep slope characteristics of tunnel FETs (TFET) has been proposed and benchmarked with 20 nm Si FinFET technology. The analysis is performed considering the parameters such as iso-area, iso-energy, iso-speed and noise margins for energy efficiency and reliability. It is clearly evident that TFET buffers exhibit improved speed of operation and high energy efficiency over FinFET buffers for scaled supply voltages, demonstrating suitability for applications such as Internet of things (IoT) SoCs. To further exemplify the buffer circuit performance, TFET/FinFET pass transistor based full adder carry circuit is implemented whose output load is driven by TFET/FinFET buffer. Unlike FinFET buffer circuits, TFET buffers prove to be reliable and energy efficient in driving larger loads despite the area overhead caused due to the unidirectional current conduction of TFETs.

Nano-scale Transistors with Circuit Interaction for Designing Energy-Efficient and Reliable Adder Cells at Low VDD

ABSTRACT Designing reliable and energy-efficient circuits with CMOS technology scaling is a pressing challenge at scaled supply voltages. This paper provides design insights and circuit interaction approach with two such emerging devices, double-gate FinFETs and tunnel field effect transistors (TFETs), for designing basic computing building blocks such as adder cells. At the circuit level, TFET-based transmission gate logic 1-bit full adder (TGLA) and improved transmission gate logic 1-bit full adder (ITGLA) cells have been proposed and designed taking into unidirectional conduction and ambipolar currents of TFETs into consideration. The performance of TFET designs has been benchmarked with 20 nm double-gate Si FinFET technology. ITGLA design is a better energy-efficient option in comparison to TGLA design with FinFETs but has reduced reliability. It has been demonstrated that the steep slope characteristics of TFETs enable both TGLA and ITGLA designs to display improved energy efficiency and reliability characteristics (in the form of reduced overshoot, reduced glitches, improved logic swing, etc.). These characteristics make TFETs desirable candidates for reliable and energy-efficient computing architectures at scaled supply voltages.