Sadulla Shaik

Tunnel FET based low voltage static vs dynamic logic families for energy efficiency

Tunnel FETs as steep slope devices have attracted attention for achieving energy efficiency at low supply voltages. This paper presents the design of Hetero-junction Tunnel FET (HTFET) based logic gates for static and dynamic logic topologies for the first time. Comparison is also done with 20nm Si FinFET technology with supply voltage scaling. Due to the steep slope characteristics, HTFET topologies have improved energy efficiency in comparison to Si FinFET configurations. It has been observed that HTFET static logic gate (two input NAND) is ~60% more energy efficient then Si FinFET static logic gate. One of the key findings from this work is that HTFET dynamic logic gates outperform HTFET static gates and FinFET designs in terms of energy efficiency due to HTFETs steep slope, low static power and reduced delay values. The HTFET dynamic logic gate has ~65% less energy consumption than HTFET static NAND gate and ~56% less energy consumption than FinFET dynamic NAND gate at Vdd=0.2V.

Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing

Tunnel FETs (TFETs) as steep slope devices have attracted much attention for designing energy efficient digital systems at scaled supply voltages. In this paper, we propose a circuit/architectural co-design approach for designing reliable and energy efficient adder cells for new computing platforms at supply voltages as low as 0.1V. At circuit level, widely used XOR gates such as 6T and 8T designs are explored and at the architectural level, adder cells with static CMOS like design (28T), tarnsmission gate design (24T), XOR based design (22T and 18T), and MUX based design (MBFA-22T) have been considered. The performance of all TFET designs have been benchmarked with 20nm double gate Si Fin FET technology. TFET designs have lower energy and energy delay product (EDP) due to TFETs steep sub threshold slope characteristics at 0.1V. 18T design is more energy efficient with slight trade-off in logic swing (i.e., robustness) and 22T and 28T designs are more robust and optimal energy efficient options.

Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs

This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFETs device level chracteristics (steep subthreshold slope, large Ion/Ioff etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, gm/Ids, BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.

Wireless solution for polyhouse cultivation using embedded system

In this paper the controlling mechanism for monitoring the environmental factors inside a polyhouse is proposed. By using this technique the ambient temperature and humidity can be controlled. These two factors are crucial for the plant growth inside a polyhouse. The prototype is designed by using AT89S52 microcontroller and tested successfully. The system can provide ideal temperature and humidity values as required for the proper growth of the plant. Using the GSM module the farmer can check the temperature inside the polyhouse from a remote location and based on the preloaded temperature values the motors and fans provide sufficient cooling and humidity inside the polyhouse. The advantage of this system lies in reducing the human effort by automation which further provides suitable environment inside the polyhouse. The installation cost is considerably less for the proposed system. For monitoring temperature inside the polyhouse LM35 temperature sensor is used because of its accuracy and fast transmission of data. SY-HS-220 humidity sensor is used for monitoring the humidity inside the polyhouse. These two sensors are integrated with the microcontroller through MCP3208Analog to digital converter. Whenever the temperature and humidity inside the polyhouse increases beyond 25°C, the motor and the fan are turned on automatically to cool the temperature, which are connected to the microcontroller by L293D. The same information about the status of temperature, humidity and motors is transmitted to the farmer and PC node through GSM Module via MAX232. Keil uVision4 cross compiler has been used for implementing the proposed system.

Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET’s steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has ∼91% smaller energy delay product (EDP) and ∼84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2V VDD.

Nano-scale Transistors with Circuit Interaction for Designing Energy-Efficient and Reliable Adder Cells at Low VDD

ABSTRACT Designing reliable and energy-efficient circuits with CMOS technology scaling is a pressing challenge at scaled supply voltages. This paper provides design insights and circuit interaction approach with two such emerging devices, double-gate FinFETs and tunnel field effect transistors (TFETs), for designing basic computing building blocks such as adder cells. At the circuit level, TFET-based transmission gate logic 1-bit full adder (TGLA) and improved transmission gate logic 1-bit full adder (ITGLA) cells have been proposed and designed taking into unidirectional conduction and ambipolar currents of TFETs into consideration. The performance of TFET designs has been benchmarked with 20 nm double-gate Si FinFET technology. ITGLA design is a better energy-efficient option in comparison to TGLA design with FinFETs but has reduced reliability. It has been demonstrated that the steep slope characteristics of TFETs enable both TGLA and ITGLA designs to display improved energy efficiency and reliability characteristics (in the form of reduced overshoot, reduced glitches, improved logic swing, etc.). These characteristics make TFETs desirable candidates for reliable and energy-efficient computing architectures at scaled supply voltages.

Performance benchmarking of tunnel transistors for energy efficient 4-bit adder architectures at low V DD

Tunnel field-effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. This paper presents design analysis and benchmarking of TFET based three different 1-bit full adders (8T-XOR Logic, 6T-XOR Logic and MUX Based) are used for designing 4-bit adders in two different topologies targeting a VDD below 500 mV. These topologies are 22T/18T 1-bit full adder based 4-bit carry propagate adder (22T/18TCPA) and multiplexer logic 1-bit full adder based 4-bit carry propagate adder (MCPA). The performance of TFET based 4-bit adder topologies has been benchmarked with 20 nm double gate Si FinFET technology. Tunnel FETs are desirable candidates for building energy efficient and reliable arithmetic blocks with supply voltage scaling. We demonstrate that TFETs steep slope characteristics enable the 22TCPA design to be energy efficient option along with improved reliability and 18TCPA design is the best in terms of energy efficiency and reliability amongst all designs at low supply voltages.

Performance evaluation of different SRAM topologies using 180, 90 and 45 nm technology

The design of various standard SRAM topologies with different technologies has been designed and tested for delay and power dissipation with respect to the different supply voltages. For this consideration, different topologies viz. 6T, 7T, 8T, 9T and 10T SRAM cells have taken. And these cells are designed using generic process development kit (gpdk) 45, 90 and 180 nm technologies. And all these are tested in cadence tool. The detailed analysis about these cells functionality and their characteristic behavior with the applied parameter of supply voltage is presented. The results of the delay, power dissipation with respect to the Vdd are plotted using MATLAB software. Also their layouts were designed and tabulated their areas.