Kain Lu Low

Electronic band structure and effective mass parameters of Ge1−xSnx alloys

This work investigates the electronic band structures of bulk Ge1-xSnx alloys using the empirical pseudopotential method (EPM) for Sn composition x varying from 0 to 0.2. The adjustable form factors of EPM were tuned in order to reproduce the band features that agree well with the reported experimental data. Based on the adjusted pseudopotential form factors, the band structures of Ge1-xSnx alloys were calculated along high symmetry lines in the Brillouin zone. The effective masses at the band edges were extracted by using a parabolic line fit. The bowing parameters of hole and electron effective masses were then derived by fitting the effective mass at different Sn compositions by a quadratic polynomial. The hole and electron effective mass were examined for bulk Ge1-xSnx alloys along specific directions or orientations on various crystal planes. In addition, employing the effective-mass Hamiltonian for diamond semiconductor, band edge dispersion at the Γ-point calculated by 8-band k.p. method was fitted...

Germanium–Tin P-Channel Tunneling Field-Effect Transistor: Device Design and Technology Demonstration

We report the demonstration of germanium-tin (GeSn) p-channel tunneling field-effect transistor (p-TFET) with good device performance in terms of on-state current (I_on). With the incorporation of Sn, the conduction band minima at Γ-point of GeSn alloy shift down, increasing the direct band-to-band tunneling (BTBT) generation rate at the source-channel tunneling junction in TFET. In addition, n-type dopant activation temperature of below 400 °C can be used in GeSn, which is much lower than that in Ge (700 °C). Therefore, n-type dopant diffusion in GeSn is suppressed leading to an abrupt n⁺ tunneling junction that is favorable for the source junction of a p-TFET. Lateral Ge_0.958Sn_0.042 p-TFETs were fabricated and high Ion of 29 μA/μm at V_GS = V_DS = -2 V and 4.34 μA/μm at V_GS = V_DS = -1 V is achieved.

Towards direct band-to-band tunneling in P-channel tunneling field effect transistor (TFET): Technology enablement by Germanium-tin (GeSn)

In this work, we report the first demonstration of GeSn pTFET. Good device characteristics were obtained. This may be attributed to direct BTBT, high hole mobility in the GeSn channel, and the formation of abruptly and heavily doped N+ source. The ION performance can be improved with further device optimization.

Germanium-tin n-channel tunneling field-effect transistor: Device physics and simulation study

We investigate germanium-tin alloy (Ge1−xSnx) as a material for the design of tunneling field-effect transistor (TFET) operating at low supply voltages. Compared with Ge, Ge1−xSnx has a smaller band-gap. The reported band-gap of Ge0.89Sn0.11 is 0.477 eV, ∼28% smaller than that of Ge. More importantly, Ge1−xSnx becomes a direct band-gap material when Sn composition x is higher than 0.11. By employing Ge1−xSnx in TFET, direct band-to-band tunneling (BTBT) is realized. Direct BTBT generally has higher tunneling probability than indirect BTBT. The drive current of TFET is boosted due to the direct BTBT and the reduced band-gap of Ge1−xSnx. Device simulations show that the drive current and subthreshold swing S characteristics of Ge1−xSnx TFETs with x ranging from 0 to 0.2 are improved by increasing the Sn composition x. For Ge0.8Sn0.2 TFET, sub-60 mV/decade S is achieved at a high current level of ∼8 μA/μm. For x higher than 0.11, Ge1−xSnx TFETs show higher on-state current ION compared to Ge TFET at a supply...

Ballistic Transport Performance of Silicane and Germanane Transistors

The ballistic transport performance of field-effect transistor (FET) based on hydrogenated silicene and germanene, i.e., silicane and germanane, respectively, is examined. The electronic band structures of silicane and germanane are investigated using the first-principles density functional theory. Subsequently, the ballistic performance of FETs is evaluated via the semiclassical ballistic transport model. We find that silicane n-MOSFET offers a relatively better ON-current performance than transistors made of germanane and 2-D transition metal dichalcogenides (2-D-TMDs) (MoS2, MoSe2, WS2, and WSe2). Germanane n-MOSFET suffers from the issue of low density of states due to its smaller electron effective mass. P-FETs based on germanane and silicane have higher ON-current than those of 2-D-TMDs p-FETs. Further investigation on other aspects of silicane and germanane MOSFETs, such as gate leakage and contact resistance, is needed to comprehensively assess their overall performance metrics.

Simulation of tunneling field-effect transistors with extended source structures

In this paper, we perform a study of novel source structures in double-gate (DG) Tunneling Field-Effect Transistors (TFETs) by two-dimensional numerical simulation of source structures in double gate tunneling field effect. Extended source structures are employed in both pure Ge TFETs and Ge-source Si-body TFETs, and on-state current enhancement is observed in simulation results. Compared with conventional p+-p−-n+ TFETs, the p+ region in extended source TFETs extends underneath the gates. When large gate bias is applied, high electric field ξ, which distributes along p+-p− junction edge extends into the middle of the channel. More tunneling paths with short lengths are available in the on-state, effectively boosting the drive current of TFET. In addition, the extent of performance enhancement depends on the geometry of the extended source. By incorporating heterojunction, TFET drive current can be increased further, which is up to 0.8 mA/μm at VGS = VDS = 0.7 V.

Device Physics and Design of a L-Shaped Germanium Source Tunneling Transistor

A novel tunneling field-effect transistor (TFET) with an L-shaped Ge source is investigated. The device comprises a Ge source that extends underneath a Si-channel region and separated from the drain by an insulator (SiO2). By optimizing the overlap length of the extended source LOV and the Si body thickness TSi, the current due to vertical band-to-band tunneling (BTBT) of the Ge–Si hetero-junction could be increased significantly and is scalable with LOV. This leads to higher ION and improved S. The SiO2 also reduces OFF-state current IOFF by blocking leakage paths. With extensive simulation, the device physics and design guidelines of this novel structure are outlined.

First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules

The first monolithic integration of Ge p-FETs and InAs n-FETs on silicon substrate using a sub-120 nm III-V buffer technology is reported. A common digital etch process was developed to precisely control the etching of InAs and Ge, enabling the realization of Ge p-FETs and InAs n-FETs with a body thickness Tbody of below 5 nm and channel lengths LCH smaller than 200 nm. Other process modules such as common gate stack and contact processes were also employed. By comparing with other reports that co-integrated Si1-xGex p-FETs and InxGa1-xAs n-FETs on Si or Ge substrates, the Ge p-FETs and InAs n-FETs in this work achieve the highest drive current ION.

PBTI characteristics of N-channel tunneling field effect transistor with HfO 2 gate dielectric: New insights and physical model

We report the first comparison study of BTI characteristics of nTFET and nMOSFET with the same high-k/metal gate stack fabricated on the same wafer. NTFETs demonstrate smaller ΔVTH and Gm loss in comparison with the nMOSFET under the same PBTI stress. We speculate that the trapped electrons density in HfO2 gate dielectric above the tunnel junction (TJ) is lower than that above the channel, which leads to the superior PBTI characteristics in nTFET.

Gate-All-Around In 0.53 Ga 0.47 As Junctionless Nanowire FET With Tapered Source/Drain Structure

A simple two step wet etch approach to fabricate nanowires (NWs) with a tapered source/drain (S/D) architecture is presented. Based on the unique NW architecture, gate-all-around junctionless NW FETs with sub-15-nm channel length (L_CH), NW height (H_NW), and NW width (W_NW) were realized. Despite having a large equivalent oxide thickness of ~4.5 nm, high extrinsic transconductance (G_m,ext) of 820 μS/μm was achieved at V_D of 0.5 V. Due to the unique tapered S/D structure, the device realized in this paper achieved S/D series resistance (R_SD) of 275 Ω · μm, which is one of the lowest among the reported 3-D InGaAs MOSFETs.