Chunlei Zhan

High-mobility germanium-tin (GeSn) P-channel MOSFETs featuring metallic source/drain and sub-370 °C process modules

We report the first demonstration of GeSn pMOSFETs. Key highlights of this work also includes a 180 °C GeSn MBE growth, sub-370 °C Si<inf>2</inf>H<inf>6</inf> surface passivation and gate stack process for GeSn, and an implantless metallic NiGeSn S/D formed at 350 °C. A hole mobility of 430 cm²/Vs is obtained for GeSn pMOSFETs, which is 66% higher than that of the Ge control pMOSFETs. GeSn pMOSFETs show a 64% lower S/D resistance as compared to the Ge control devices.

Silicon-based tunneling field-effect transistor with elevated germanium source formed on (110) silicon substrate

Si-based tunneling field-effect transistors (TFETs) with elevated Ge source were fabricated on Si(110) substrate. The in situ B-doped Ge (Ge:B) source grown on Si(110) has a substitutional B concentration up to 7.8×1020 cm−3, that is more than one order of magnitude higher than that in Ge grown on Si(100) under the same growth conditions. Ge:B epitaxy on (110) and (100) Si is discussed. The TFET with elevated Ge source formed on Si(110) has a subthreshold swing of 85 mV/decade, which is a substantial improvement over that of the control TFET formed on Si(100). This is attributed to the high B doping concentration in the Ge:B(110) source as well as the band gap narrowing effect.

Source Engineering for Tunnel Field-Effect Transistor: Elevated Source with Vertical Silicon?Germanium/Germanium Heterostructure

In this work, we demonstrate by simulation and experiment that the performance of a p+ Si0.5Ge0.5 source tunnel field-effect transistor (TFET) can be improved by inserting an undoped Ge layer between source and channel. The Ge layer suppresses diffusion of boron into the Si channel and it also forms a Si0.5Ge0.5/Ge/Si hole quantum well, leading to an abrupt boron profile and a high hole concentration at the source edge. At the Ge/Si heterojunction, the presence of compressive strain in the Ge layer increases the valence band offset, while the tensile strain in the Si channel increases the conduction band offset, which effectively reduces the tunnel barrier and enhances the tunnel probability. Compared with a control device without the Ge layer, TFETs with a Si0.5Ge0.5/Ge source show a higher on-state current ION and improved threshold voltage VTH and subthreshold characteristics.

Enhancement of TFET performance using dopant profile-steepening implant and source dopant concentration engineering at tunneling junction

All-Silicon Tunneling Field Effect Transistors (TFETs) with relatively high Ion values were fabricated by inserting an N+ pocket between source and channel to achieve sharpening or steepening of the source dopant profile. The source-side pocket or Dopant Profile Steepening Implant (DPSI) can be tuned to engineer the junction abruptness, boost the lateral electric field at the tunnel region, and reduce the tunneling width for Ion enhancement. By designing the DPSI dose and energy, we demonstrate that further enhancement in Ion values can be achieved.

Simulation of tunneling field-effect transistors with extended source structures

In this paper, we perform a study of novel source structures in double-gate (DG) Tunneling Field-Effect Transistors (TFETs) by two-dimensional numerical simulation of source structures in double gate tunneling field effect. Extended source structures are employed in both pure Ge TFETs and Ge-source Si-body TFETs, and on-state current enhancement is observed in simulation results. Compared with conventional p+-p−-n+ TFETs, the p+ region in extended source TFETs extends underneath the gates. When large gate bias is applied, high electric field ξ, which distributes along p+-p− junction edge extends into the middle of the channel. More tunneling paths with short lengths are available in the on-state, effectively boosting the drive current of TFET. In addition, the extent of performance enhancement depends on the geometry of the extended source. By incorporating heterojunction, TFET drive current can be increased further, which is up to 0.8 mA/μm at VGS = VDS = 0.7 V.

Device Physics and Design of a L-Shaped Germanium Source Tunneling Transistor

A novel tunneling field-effect transistor (TFET) with an L-shaped Ge source is investigated. The device comprises a Ge source that extends underneath a Si-channel region and separated from the drain by an insulator (SiO2). By optimizing the overlap length of the extended source LOV and the Si body thickness TSi, the current due to vertical band-to-band tunneling (BTBT) of the Ge–Si hetero-junction could be increased significantly and is scalable with LOV. This leads to higher ION and improved S. The SiO2 also reduces OFF-state current IOFF by blocking leakage paths. With extensive simulation, the device physics and design guidelines of this novel structure are outlined.

Germanium Multiple-Gate Field-Effect Transistors Formed on Germanium-on-Insulator Substrate

We demonstrate the integration of high performance p-channel Germanium Multiple-Gate Field-Effect Transistors (MuGFETs) on a Germanium-on-Insulator substrate. Detailed process conditions are documented in this paper. The effects of Ge fin doping concentration on the electrical performance of Ge MuGFETs are discussed, and this could be useful for further device optimization. It is found that a higher fin doping leads to better control of short-channel efforts of Ge MuGFETs but degrades the on-state current and transconductance. High on-state current for Ge MuGFETs is reported in this paper.

Germanium Multiple-Gate Field-Effect Transistor With In Situ Boron-Doped Raised Source/Drain

We report the first demonstration of a p-channel Ω-gate Germanium (Ge) multiple-gate field-effect transistor (MuGFET) on a Germanium-on-Insulator (GeOI) substrate with in situ Boron (B)-doped Ge (Ge:B) raised source/drain (RSD). Detailed process optimization on epitaxial growth of Ge on patterned GeOI samples is discussed. Process integration of Ge:B RSD into Ge MuGFETs using a CMOS compatible process flow is documented. Electrical characteristics of Ge MuGFETs with RSD are reported.

PBTI characteristics of N-channel tunneling field effect transistor with HfO 2 gate dielectric: New insights and physical model

We report the first comparison study of BTI characteristics of nTFET and nMOSFET with the same high-k/metal gate stack fabricated on the same wafer. NTFETs demonstrate smaller ΔVTH and Gm loss in comparison with the nMOSFET under the same PBTI stress. We speculate that the trapped electrons density in HfO2 gate dielectric above the tunnel junction (TJ) is lower than that above the channel, which leads to the superior PBTI characteristics in nTFET.

Bias temperature instability (BTI) characteristics of graphene Field-Effect Transistors

We report a bias temperature instability (BTI) study of graphene Field-Effect Transistor (G-FET) for the first time. New BTI characteristics are observed for G-FETs fabricated using a graphene transfer-free process. Temperature significantly affects BTI of G-FETs by changing the direction of shift of IDS. A plausible graphene BTI mechanism is discussed.