Kaiwei Yao

Tapped-inductor buck converter for high-step-down DC-DC conversion

The narrow duty cycle in the buck converter limits its application for high-step-down dc-dc conversion. With a simple structure, the tapped-inductor buck converter shows promise for extending the duty cycle. However, the leakage inductance causes a huge turn-off voltage spike across the top switch. Also, the gate drive for the top switch is not simple due to its floating source connection. This paper solves all these problems by modifying the tapped-inductor structure. A simple lossless clamp circuit can effectively clamp the switch turn-off voltage spike and totally recover the leakage energy. Experimental results for 12V-to-1.5V and 48V-to-6V dc-dc conversions show significant improvements in efficiency.

A novel resonant gate driver for high frequency synchronous buck converters

This paper introduces a new resonant gate driver for both the top and bottom switches of a synchronous buck converter. A coupled inductor is used to reduce the size as well as to transfer energy between the top and bottom gate driving. A possible semiconductor integration approach is proposed for this resonant gate driver based on a self-adaptive control method. Theoretical analysis, simulation and experimental results prove that the proposed driver can greatly reduce the gate driving loss and that it is well suited to high-frequency applications.

Comparison of three topology candidates for 12 V VRM

Most of todays voltage regulation modules (VRMs) draw power from 5 V output of the silver box. For future applications, this voltage bus will be too low to be practical. In the future, distributed power systems (DPS) with 12 V or 48 V voltage bus, are more attractive solutions for servers and high-end workstations. This paper focuses primarily on the comparison of three 12 V VRM topology candidates: buck; tapped-inductor buck; and active-clamp couple-buck.

A novel winding-coupled buck converter for high-frequency, high-step-down DC-DC conversion

This paper analyzes the fundamental limitations of the buck converter for high-frequency, high-step-down dc-dc conversion. Further modification with additional coupled windings in the buck converter yields a novel topology, which significantly improves the efficiency without compromising the transient response. An integrated magnetic structure is proposed for these windings so that the same magnetic cores used in the buck converter can be used here as well. Furthermore, it is easy to implement a lossless clamp circuit to limit the device voltage stress and to recover inductor leakage energy. This new topology is applied for a 12V-to-1.5V/25A voltage regulator module (VRM) design. At a switching frequency of 2MHz, over 80% full-load efficiency is achieved, which is 8% higher than that of the conventional buck converter.

Optimal design of the active droop control method for the transient response

Use of the active droop control method is a popular way to achieve adaptive voltage position (AVP) for the voltage regulator (VR). This paper discusses the small-signal model of the active droop control method, which is shown to be a two-loop feedback control system. The compensator design impacts both the current and voltage loops, making the design complicated. An optimal design method is proposed in order to achieve equal crossover frequencies for the two loops so that constant output impedance is realized in the VR. Simulation and experimental results prove the good VR transient response and high efficiency.

Analysis of the power delivery path from the 12-V VR to the microprocessor

This paper offers a thorough analysis of the power delivery path. Based on the power delivery path model, the current slew rate of each loop is derived. The relationship between the inductor current slew rate of the voltage regulator (VR) and the bandwidth is also derived. Then, the level of the voltage spike across the capacitors of each loop is determined, after which the relationship between the bandwidth and the capacitance can be plotted. We find that for todays power delivery structure, the bulk capacitors can be eliminated as long as the bandwidth is pushed beyond 350 kHz. The experimental results of a 2-MHz two-stage 12-V VR verify this analysis.

Two-stage approach for 12-V VR

To meet the stringent specifications of the voltage regulator (VR), the two-stage approach is proposed for the 12-V VR. This paper discusses detailed design considerations, which include the design of the first stage, optimization of the intermediate bus voltage, design of the intermediate bus capacitors, and the design of the ultra-high frequency second stage. The analysis shows that the two-stage approach can realize high frequency, thus significantly reducing the output capacitance and therefore decreasing the cost. A 1.2-V/100-A prototype is built to verify the analysis. The second stage runs at 2MHz per phase and the total efficiency is as high as 81%. Compared to the conventional single-stage multiphase buck, the two-stage approach is more cost-effective and more efficient.

Critical bandwidth for the load transient response of voltage regulator modules

This paper investigates the relationship between the control bandwidth and the load transient response in voltage regulator modules (VRMs), which are designed with multiphase interleaving synchronous buck converters. Both voltage- and current-mode controls are discussed. A critical bandwidth value is discovered, beyond which pushing the bandwidth can no longer reduce the output voltage spike during the load transient response. Also, the critical bandwidths are different according to different kinds of output capacitors. The critical bandwidth concept highlights the trend of high-frequency VRM design that uses ceramic capacitors to achieve smaller size and faster load transient response. Simulation and experimental results prove the theoretical analysis.

Two-stage approach for 12 V VR

To meet the stringent specifications of the voltage regulator (VR), the two-stage approach is proposed for the 12 V VR. This paper discusses detailed design considerations, which include the design of the first stage, optimization of the intermediate bus voltage, design of the intermediate bus capacitors, and the design of the ultra-high frequency second stage. The analysis shows that the two-stage approach can realize high frequency, thus significantly reducing the output capacitance and therefore decreasing the cost. A 1.2 V/100 A prototype is built to verify the analysis. The second stage runs at 2 MHz per phase and the total efficiency is as high as 81%. Compared to the conventional single-stage multi phase buck, the two-stage approach is more cost effective and more efficient.

Adaptive voltage position design for voltage regulators

This paper proposes a general design guideline for the voltage regulator (VR) to achieve adaptive voltage position (AVP). All existing control methods are covered for different kinds of output filter capacitors. Based on the small-signal model analysis, the output impedance and system control bandwidth are discussed. Following the proposed design guidelines, simulation and experimental results demonstrate very good VR transient response.