Kamal Chaudhary

Computing the area versus delay trade-off curves in technology mapping

We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps. In the first step, we compute delay functions (which capture gate area-arrival time tradeoffs) at all nodes in the network, and in the second step we generate the mapping solution based on the computed delay functions and the required times at the primary outputs. For a NAND-decomposed tree, subject to load calculation errors, this two-step approach finds the minimum area mapping satisfying a delay constraint if such solution exists. The algorithm has polynomial run time on a node-balanced tree and is easily extended to mapping a directed acyclic graph (DAG). We also show how to account for the wire delays during the delay function computation step. Our results compare favorably with those of MIS2.2 mapper.

Post-placement residual-overlap removal with minimal movement

In this paper we present a novel approach for removing residual overlaps among blocks. We start out by representing the placement in the sequence pair form and describe transformations to the sequence pair to make the placement feasible. This is followed by a distance-based slack allocation to generate a new placement with no overlaps, while being as close to the original placement as possible. Our results demonstrate the efficacy of our approach in transforming layouts with overlaps to overlap-free layouts with minimal object movement.

Technology Mapping Using Fuzzy Logic

This paper presents a placement-driven technology mapping procedure based on fuzzy delay curves. The fuzziness has been introduced to deal with the inherent vagueness in wiring loads (derived from a dynamically updated placement) and used by the mapper to calculate the signal arrival times. In the process we describe a number of fuzzy operations which are needed to generate the fuzzy delay curves and to select a minimum area mapping solution satisfying a set of timing constraints. This procedure has been implemented and the results are on average 1% and 26% (5% and 3%)better in terms of area and delay compared to a technology mapping procedure with zero (crisp) wire load values.

Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs

Platform FPGAs have introduced complex reconfigurable black-boxes for complete system on chip implementation. With rising expectations from these architectures there is a need to perform optimizations across the FPGA slice fabric and the newly introduced black boxes to maximize performance gains. In this paper, we discuss a timing driven reconfiguration technique to improve performance of DSP designs on platform FPGAs by (i) optimal register placement algorithms within the DSP 48 block and (ii) timing driven mechanism to have maximal pipeline depth.