Kambiz Moez

A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications

To employ the distributed amplification technique for the design of ultra-wide-band low-noise amplifiers, the poor noise performance of the conventional distributed amplifiers (DAs) needs to be improved. In this work, the terminating resistor of the gate transmission line, a main contributor to the overall DAs noise figure, is replaced with a resistive-inductive network. The proposed terminating network creates an intentional mismatch to reduce the noise contribution of the terminating network. The degraded input matching at low frequencies can be tolerated for ultra-wide-band applications as they need to operate above 3 GHz. Implemented in a 0.13 mum CMOS process, the proposed DA achieves a flat gain of 12 dB with an average noise figure of 3.3 dB over the 3- to 9.4-GHz band, the best reported noise performance for a CMOS DA in the literature. The amplifier dissipates 30 mW from two 0.6-V and 1-V dc power supplies.

A 324-Element Vivaldi Antenna Array for Radio Astronomy Instrumentation

This paper presents a 324-element 2-D broadside array for radio astronomy instrumentation which is sensitive to two mutually orthogonal polarizations. The array is composed of cruciform units consisting of a group of four Vivaldi antennas arranged in a cross-shaped structure. The Vivaldi antenna used in this array exhibits a radiation intensity characteristic with a symmetrical main beam of 87.5° at 3 GHz and 44.2° at 6 GHz. The measured maximum side/backlobe level is 10.3 dB below the main beam level. The array can operate at a high frequency of 5.4 GHz without the formation of grating lobes.

Hybrid Forward and Backward Threshold-Compensated RF-DC Power Converter for RF Energy Harvesting

This paper presents a hybrid forward and backward threshold voltage compensated radio-frequency to direct current (RF-to-DC) power conversion circuit for RF energy harvesting applications. The proposed circuit uses standard p-channel metal-oxide semiconductor transistors in all the stages except for the first few stages to allow individual body biasing eliminating the need for triple-well technology in the previously reported forward compensation schemes. Two different RF-DC power conversion circuits, one optimized to provide high power conversion efficiency (PCE) and the other to produce a large output DC voltage harvested from extremely low input power levels, are designed and fabricated in IBMs 0.13 μm complementary metal-oxide-semiconductor technology. The first circuit exhibits a measured maximum PCE of 22.6% at -16.8 dBm (20.9 μW) and produces 1 V across a 1 MΩ load from a remarkably low input power level of -21.6 dBm (6.9 μW) while the latter circuit produces 2.8 V across a 1 MΩ load from a peak-to-peak input voltage of 170 mV achieving a voltage multiplication ratio of 17. Also, design strategies are developed to enhance the output DC voltage and to optimize the PCE of threshold voltage compensated voltage multiplier.

Gain-Enhanced Distributed Amplifier Using Negative Capacitance

This paper presents a new high-gain structure for the distributed amplifier. Negative capacitance cells are exploited to ameliorate the loading effects of parasitic capacitors of gain cells in order to improve the gain of the distributed amplifier while keeping the desired bandwidth. In addition, the negative capacitance circuit creates a negative resistance that can be used to increase the amplifier bandwidth. Implemented in 0.13-μm IBMs CMRF8SF CMOS, the proposed six-stage distributed amplifier presents an average gain of 13.2 dB over a bandwidth of 29.4 GHz. The measured input return loss is less than -9 dB and the output return loss is less than -9.5 dB over the entire bandwidth. With a chip area of 1.5 mm × 0.8 mm, the amplifier consumes 136 mW from a 1.5-V dc power supply.

An Area-Efficient Multistage 3.0- to 8.5-GHz CMOS UWB LNA Using Tunable Active Inductors

An area-efficient multistage 3.0- to 8.5-GHz ultrawideband low-noise amplifier (LNA) utilizing tunable active inductors (AIs) is presented. The AI includes a negative impedance circuit (NIC) consisting of a pair of cross-coupled NMOS transistors and is tuned to vary the gain and bandwidth (BW) of the amplifier. Fabricated in a 90-nm digital CMOS process, the proposed fully on-chip LNA occupies a core chip area of only 0.022 mm2. The measurement results show a power gain S21 of 16.0 dB, a noise figure of 3.1-4.4 dB, and an input return loss S11 of less than -10.5 dB over the 3-dB BW of 3.0-8.5 GHz. Tuning the AIs allows one to increase the gain above 18.0 dB and to extend the BW over 9.4 GHz. The LNA consumes 16.0 mW from a power supply of 1.2 V.

A 3.2 V –15 dBm Adaptive Threshold-Voltage Compensated RF Energy Harvester in 130 nm CMOS

This paper presents an adaptive RF-DC power converter designed to efficiently convert RF signals to DC voltages utilizing auxiliary transistors to control the threshold voltage of the transistors in the main rectifier chain dynamically. The proposed circuit passively reduces the threshold voltage of the forward-biased transistors to increase the harvested power and the output voltage and increases the threshold voltage of the reverse-biased transistors to reduce the leakage current to prevent the loss of previously stored energy. A 12-stage adaptive threshold-compensated rectifier is designed and implemented in IBMs 0.13 μm CMOS technology. The proposed rectifier exhibits measured maximum power conversion efficiency (PCE) of 32% at -15 dBm (32 μW) of input power while delivering 3.2 V to a 1 M Ω load. At a remarkably low input power of -20.5 dBm (8.9 μW) for a 1 M Ω load, the rectifier produces an output voltage of 1 V.

A 10dB 44GHz Loss-Compensated CMOS Distributed Amplifier

An 8-stage distributed amplifier (DA) suitable for 40Gb/s optical communication is implemented in a 0.13mum CMOS process. The losses of on-chip transmission lines are compensated by active negative resistors. The DA achieves a flat gain of 10dB from DC to 44GHz with an input and output matching better than -8dB. The core DA and loss compensation circuitry dissipate 44mW and 59mW, respectively.

A CMOS 2.0–11.2 GHz UWB LNA using active inductor circuit

A fully-active low-noise amplifier (LNA) for ultra-wideband application is presented. Passive on-chip inductor of conventional LNA design is replaced by low-noise active inductor, significantly reducing the total chip area of the proposed CMOS LNA. The core LNA circuit is a cascoded common-source amplifier loaded with an active inductor. Two buffer stages are used to provide the required input and output impedance matching. The amplifier is designed and simulated in 0.13-mum RF CMOS process. It exhibits a forward gain (S21) of 11.2 dB, a noise figure (NF) of 2.2-4.0 dB, and return losses (S11 and S22) of less than -10 dB over the frequency range of 2.0 to 11.2 GHz while consuming only 13.5 mW from a power supply of 1.5 V. The proposed amplifier occupies 0.09 mm of chip area.

A New Loss Compensation Technique for CMOS Distributed Amplifiers

This brief presents a circuit technique to compensate for the metal and substrate loss of the on-chip transmission lines (TLs), and, consequently, to improve the gain flatness and bandwidth of CMOS distributed amplifiers (DAs). An eight-stage DA suitable for 40-Gb/s optical communication is devised and implemented in a 0.13-mum CMOS process. The DA achieves a flat gain of 10 dB from dc to 44 GHz with an input and output matching better than -8 dB. The measured noise figure varies from 2.5 to 7.5 dB with the amplifiers band. The proposed DA dissipates 103 mW from two 1-V and 1.2-V dc supplies.

A novel 0.6V CMOS folded Gilbert-cell mixer for UWB applications

A novel CMOS wideband mixer operating with only 0.6 V power supply has been designed. Such low-voltage operation is achieved by reducing threshold voltage (VTH) of the switching transistors in the folded Gilbert cell multiplier. For input RF frequency range of 3.5-8.0 GHz and IF range of 20 MHz-2.5 GHz, the 50 W impedance matched condition is achieved, which make the proposed mixer suitable for UWB applications. The complete on-chip mixer is designed in 0.18-mum RF CMOS process. The proposed mixer exhibits a conversion gain of 11.0-5.5 dB, SSB noise-figure (NF) of 8.0-10.0 dB, and return losses (S11and S22) of less than -10 dB over frequency of 3.5-6.5 GHz. The circuit consumes only 3.75 mW from the DC power supply of 0.6 V.