Md. Mahbub Reja

Noncontact wafer probe using wireless probe cards

A method for wireless, noncontact testing of semiconductor wafers is presented. The technology applies to chips with active electronics, including standard integrated circuits (ICs), which require testing at the wafer level. The technology relies on short-range, near field communications to transfer data at gigabit per second rates between the probe card and the device under test (DUT) on a wafer. The probe consists of a CMOS device with micro antenna structures and transceiver circuits. Each antenna and transceiver circuit is capable of probing one input/output (I/O) site on the DUT. Each I/O site on the DUT is connected to a single antennae and transceiver circuit, which is designed into the DUT. The antennae and transceiver circuits can be incorporated into the DUT without any impact on performance or real estate. The main advantage of noncontact wafer probing is higher reliability (less retest, no pad scrub marks), added functionality (higher test frequencies at higher pin densities), and increased throughput (higher parallelism, reduced alignment tolerance, less maintenance, and less downtime). The wireless probes interface to standard automated test equipment (ATE) while all antenna structures and electronics needed on the DUT are fully CMOS compliant

High throughput non-contact SiP testing

A non-contact method for parallel testing of system-in-package (SiP) assemblies is presented. This technology allows for JTAG testing of partially or fully populated SiPs in wafer form, in advance of final packaging. The technology utilizes non-contact GHz short-range, near field communications to transfer bi-directional data to SiP substrates; creating a wireless test access port or WTAP. The system is integrated with a standard probe card to deliver power and wireless signals. The wireless probes convert high frequency RF (GHz) transceiver signals to standard tester ATE logic levels and allow the use of standard probers and JTAG testers. In addition, all transceivers (DUTand probe) use antenna structures and electronics that are fully CMOS compliant. Enhancing the economics of SiP manufacture by enabling parallel non-contact testing of SiPs before packaging is a key benefit of this technology.

An Area-Efficient Multistage 3.0- to 8.5-GHz CMOS UWB LNA Using Tunable Active Inductors

An area-efficient multistage 3.0- to 8.5-GHz ultrawideband low-noise amplifier (LNA) utilizing tunable active inductors (AIs) is presented. The AI includes a negative impedance circuit (NIC) consisting of a pair of cross-coupled NMOS transistors and is tuned to vary the gain and bandwidth (BW) of the amplifier. Fabricated in a 90-nm digital CMOS process, the proposed fully on-chip LNA occupies a core chip area of only 0.022 mm2. The measurement results show a power gain S21 of 16.0 dB, a noise figure of 3.1-4.4 dB, and an input return loss S11 of less than -10.5 dB over the 3-dB BW of 3.0-8.5 GHz. Tuning the AIs allows one to increase the gain above 18.0 dB and to extend the BW over 9.4 GHz. The LNA consumes 16.0 mW from a power supply of 1.2 V.

A CMOS 2.0–11.2 GHz UWB LNA using active inductor circuit

A fully-active low-noise amplifier (LNA) for ultra-wideband application is presented. Passive on-chip inductor of conventional LNA design is replaced by low-noise active inductor, significantly reducing the total chip area of the proposed CMOS LNA. The core LNA circuit is a cascoded common-source amplifier loaded with an active inductor. Two buffer stages are used to provide the required input and output impedance matching. The amplifier is designed and simulated in 0.13-mum RF CMOS process. It exhibits a forward gain (S21) of 11.2 dB, a noise figure (NF) of 2.2-4.0 dB, and return losses (S11 and S22) of less than -10 dB over the frequency range of 2.0 to 11.2 GHz while consuming only 13.5 mW from a power supply of 1.5 V. The proposed amplifier occupies 0.09 mm of chip area.

A novel 0.6V CMOS folded Gilbert-cell mixer for UWB applications

A novel CMOS wideband mixer operating with only 0.6 V power supply has been designed. Such low-voltage operation is achieved by reducing threshold voltage (VTH) of the switching transistors in the folded Gilbert cell multiplier. For input RF frequency range of 3.5-8.0 GHz and IF range of 20 MHz-2.5 GHz, the 50 W impedance matched condition is achieved, which make the proposed mixer suitable for UWB applications. The complete on-chip mixer is designed in 0.18-mum RF CMOS process. The proposed mixer exhibits a conversion gain of 11.0-5.5 dB, SSB noise-figure (NF) of 8.0-10.0 dB, and return losses (S11and S22) of less than -10 dB over frequency of 3.5-6.5 GHz. The circuit consumes only 3.75 mW from the DC power supply of 0.6 V.

Non-contact Testing for SoC and RCP (SIPs) at Advanced Nodes

Non-contact methods for testing system-on-chip (SoC) and system in package (SIP) assemblies are presented. This method allows for high speed testing at the wafer level for SoCs as well as testing during and after assembly for panel or wafer level SIP technologies. Wafer testing at advanced nodes is carried out without damaging underlying metallurgy - an issue with current contact testing techniques. The technology utilizes non-contact GHz short-range transceivers to transfer test signals and results to and from SoC ICs. The wireless probes convert standard tester ATE logic levels to high frequency RF (GHz) transceiver signals and thus allow the use of standard test equipment. A reduced set of contact probes are used for test power only. A 45 nm fully CMOS compatible IC with wireless test transceivers is designed and fabricated. Enhancing the reliability and economics of IC manufacture by enabling non-contact testing of SoCs before and during packaging is a key benefit of this technology.

A wide frequency range CMOS active inductor for UWB bandpass filters

A CMOS active inductor that exhibits wide-frequency range inductive impedance with a high quality factor (Q) is presented. The inductor is designed using negative impedance obtained in a cross-coupled transistor pair that is a part of the feedback loop consisting of common gate and common drain stages. Then, a tunable ultra-wideband (UWB) bandpass filter (BPF) is designed by cascading two such inductors back-to-back through a varactor. The proposed active inductor and the BPF are designed and simulated in 90nm CMOS digital process. The inductor exhibits inductive impedance in the range from few MHz to over than 20GHz and achieves Q-factor of 600. The designed BPF shows a −3dB bandwidth of 2.25GHz with a tuning range of 5GHz.

A compact CMOS UWB LNA using tunable active inductors for WLAN interference rejection

A compact 2.0–11.0GHz CMOS ultra-wideband (UWB) low-noise amplifier (LNA) using tunable active inductors for suppressing in-band (over 4.8–6.0GHz) WLAN interference signals is presented. In the proposed LNA, the active inductor in series with a small capacitor forms an active LC resonator which rejects or notches the undesired signals at the resonance frequency. Employing multiple resonators in the LNA increases the rejection depth. Moreover, the tunability of the active inductors allows for notching the signals over a wide frequency range. Designed and simulated in a 90nm digital CMOS process, the proposed LNA with such active inductors used in notch filters occupies a core chip-area of only 0.0182mm2. The LNA exhibits an average power gain of 16.5dB over 2.0–11.0GHz bandwidth while the rejection of unwanted WLAN interference signals is −44.8dB at 5.81GHz. The notch-frequency can be tuned in excess of 4.5–6.6GHz, and the rejection depth can be increased to −87.5dB, the highest rejection among the reported notch-filter UWB LNAs.

Structural Design of a CMOS Full Low Dropout Voltage Regulator

The paper describes structural design of a full (complete) low dropout (LDO) voltage regulator. This LDO is using the following basic subcircuits: bandgap reference (BGR), folded-cascode current operational amplifier (COA), and bias circuit. The regulator is divided in three main blocks, namely, a sub-regulator generating power supply voltage for the BGR, a scaling amplifier providing convenient reference voltage for the LDO, and the LDO itself providing the required output voltage. Each block is consisting of a COA, pass transistor and resistor and represents a dedicated feedback loop. The regulator does not require any on-chip compensation capacitors, and ensures stable operation for a very wide range of capacitive loads. The complete LDO regulator is realized in standard digital 0.13-mum CMOS process for the output voltage of 1.22 V from 1.8-3.3 V power supply.

New non-gyrator type active inductors with applications

Active inductors based on a floating capacitor connected between two controlled current sources are considered. The first source controlled by the circuit input voltage supplies a current to the capacitor and develops the voltage on the capacitor shifted by 90o degrees with respect to this first current. This capacitor voltage is controlling the second current source, and due to this last control the circuit input current, besides inductive, has an active component. If a third current source also controlled by the input voltage compensates the active component then the current seen by the input voltage source becomes purely inductive. This simplified model allows one to obtain new realizations of active inductors and improve control of the inductance Q-factor. In the well-known active inductor the compensation is achieved by addition of one transistor only to the existing circuit. The overcompensation results in a very low power inductor-less oscillator. The examples of realization for 2 to 5 GHz range are given.