Kambiz Rahimi

Minimizing peak power in synchronous logic circuits

Minimizing peak power decreases the probability of failure due to hot carrier effects and electromigration. It also reduces the maximum IR voltage drop, the magnitude of substrate noise, and packaging costs. In mobile applications, minimizing peak power can help reduce the battery size. In synchronous circuits the peak power draw is correlated with clock transitions when the entire clock distribution network, all of the flip-flops and their immediate fanout switch simultaneously. In this paper, we propose an efficient, deterministic method for finding the optimal distribution of clock latencies for minimizing peak power consumption. Our algorithm spreads the clock transitions using timing slacks on non-critical paths and preserves the circuit performance. We validate our method by transistor level simulations on benchmark circuits. These experiments show that our method can reduce the peak power consumption up to 55 percent in circuits whose peak power is due to simultaneous clock transitions.

Design and Application of Adaptive Delay Sequential Elements

Lower operating voltages and faster clock frequencies in advanced fabrication processes increase the circuit delay sensitivity to voltage, temperature, and process variations and modeling approximations. Uncorrelated delay variations along data and clock paths cause timing violations. In this paper, we propose a method for correcting timing violations by in-circuit tuning of clock latencies after fabrication. We introduce adaptive delay sequential elements (ADSEs) that use charge storage on pMOS floating gates to tune the clock latencies of timing critical flip-flops. ADSEs facilitate in-circuit optimization of clock latencies under varying operating conditions. ADSE tuned clock latencies are nonvolatile and can be repeatedly adjusted after fabrication using only electrical signals. We present examples of implicit and explicit pulsed ADSEs and their tuning operations. Our experiments with fabricated prototypes show that ADSEs can tune their clock latencies with picosecond resolution over one-half of the clock period. Our experiments also show that ADSE sensitivities to supply voltage, temperature, noise, and transistor mismatch are comparable to nonadaptive sequential elements. We present experimental data that show ADSE tuned delays change only 15% after ten years at 125degC. We propose a method for selective tuning of embedded ADSEs and demonstrate its application in a fabricated prototype. ADSEs can selectively replace timing-critical flip-flops of a circuit with negligible area impact