Yanjun Ma

Highly Reliable 90-nm Logic Multitime Programmable NVM Cells Using Novel Work-Function-Engineered Tunneling Devices

A highly reliable embedded logic multitime-programmable nonvolatile memory (NVM) has been developed in a standard 90-nm logic process with no process changes and a zero-mask adder. By using a novel work-function-engineered tunneling device and 70-Aring tunneling oxide, an excellent endurance of more than 500 k cycles has been achieved. Reliability of the NVM is evaluated against the traditional tunneling device, and a model is proposed to explain the observed reliability differences. Process manufacturability on retention has also been demonstrated over process variations on the thickness of silicide-blocking layers.

Floating-Gate Nonvolatile Memory With Ultrathin 5-nm Tunnel Oxide

Reliability results of floating-gate (FG) memory using 5-nm tunnel oxides in mature (0.25 mum) to advanced (65 nm) logic processes from multiple foundries are reported. Good intrinsic retention is seen across the process nodes studied and for gate oxides as thin as 4.8 nm. With differential memory cells, we also demonstrate promising reliability results with respect to program-cycle-induced tail bits. We conclude that it is possible to develop a small-bit-count FG nonvolatile memory (NVM) array using 5-nm oxide, enabling embedded logic NVM in advanced CMOS processes with no additional masks or processing steps.

Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond

Logic NVM using I/O gate oxide as storage floating gate dielectric developed in baseline logic process does not require extra masks or process steps. Conventional wisdom has suggested that the tunnel oxide of Flash will reach its scaling limits at 6-7 nm due to high reliability requirement for high-density applications. Will FG logic NVM be scalable with tunneling oxide down to 50 A of 2.5 V I/O devices at technology nodes of 65 nm and beyond? In this work, we demonstrate that FG logic NVM with 50 A is readily achievable by performing theoretical statistics analysis and utilizing advanced reliability engineering. Reliability data on FG logic NVM with 50 A tunneling oxide in a standard 65 nm CMOS technology process is also provided.

Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory

Some researchers have previously reported that silicide-blocking layers play a key role in retaining charge in embedded DRAM and Flash memory technologies. In this paper, we investigate the retention characteristics for silicided and unsilicided floating gates embedded logic NVM fabricated in a standard 0.25/spl mu/m logic process. In contrast to previous reports, it is found in this work that silicided and unsilicided NVM have equivalent retention for cycled and un-cycled arrays with temperature bake up to 6120 hrs at 135/spl deg/C. As a result, there is more flexibility in optimizing the memory cell area for logic NVM by removing the silicide-blocking layer.

Reliability and Qualification of a Floating Gate Memory Manufactured in a Generic Logic Process for RFID Applications

In this paper, we discuss the reliability evaluation and qualification results of a small (~ 256b) pFET based floating gate nonvolatile memory for embedded application in a UHF RFID chip that is being volume produced using a foundry logic CMOS process. The memory is based on bi-directional Fowler-Nordheim tunneling using a ~65-70 Aring oxide that is available from typical foundry processes with 3.3V I/O transistors. Well over one year of retention bake data are reported to show that the memory is reliable for the required applications

Study of stress-induced leakage current and charge loss of nonvolatile memory cell with 70 /spl Aring/ tunnel oxide using floating-gate integrator technique

Techniques for measuring very low tunneling currents are critical for studying gate dielectric properties in MOSFETs, especially charge-loss mechanisms in nonvolatile memory (NVM) devices. Being able to measure stress-induced leakage current (SILC) at the floating gate operating conditions can be used to accurately extract the retention lifetime of floating gate memories. In this work, we utilize a floating-gate integrator technique (capable of resolving currents as low as 3/spl times/10/sup -22/ A) to study the effect of SILC on the charge-retention of logic NVM cells with a 70 /spl Aring/ tunnel oxide, with up to 300 k endurance cycles. The relation between SILC and V/sub ox/ is used to extrapolate the retention lifetime of the memory cell. A conservative estimate of over 10 years retention is found for logic NVM with 70 /spl Aring/ gate tunnel oxides.