Kamel Smiri

Platform based design for a multimedia Motion JPEG decoder case study

In recent years, computational requirements for embedded applications are increasing exponentially. This complexity, coupled with constantly evolving specifications, has forced designers to consider intrinsically flexible implementations. For this reason, heterogeneous multiprocessor architectural platforms are gaining prevalence for embedded systems. Deploying applications typical of multimedia domains is difficult, not only due to the heterogeneous parallelism in the platforms, but also due to the performance constraints that typify these systems. In this paradigm, the digital system-on-a-chip (SoC) platform-based design environment for shared memory multiple instructions multiple data (MIMD) architectures (Disydent) is used. The applicability of the Disydent design flow to systems in the multimedia domain is illustrated. The case studied consists in deploying a motion JPEG decoder application onto a configurable prototype of a multiprocessor MIPS platform architecture.

Fault-Tolerant in Embedded Systems (MPSoC): Performance estimation and dynamic migration tasks

Multiprocessor Systems-on-Chip (MPSoC) allow the implementation of heterogeneous architectures with a high integration capacity. In recent years, computational requirements MPSoC are increasing exponentially. This complexity, coupled with constantly evolving specifications, has forced designers to consider intrinsically flexible implementations. Deploying applications typical of multimedia domains is difficult, not only due to the heterogeneous parallelism in the platforms, but also due to the performance constraints that typify these systems. An application can be modeled as a set of cooperative tasks. A task can be implemented in software or in hardware depending on its complexity and the involved cost. Our proposal is a fault tolerance approach which combines the results of a performance model and a technicals fault tolerance. We interest of the dynamic migration task to resolve the Fault-Tolerant for Multiprocessors Embedded System.

A New profiling and pipelining approach for HEVC Decoder on ZedBoard Platform

Corresponding Author: Habib Smei, Université de Tunis El Manar, Faculté des Sciences de Tunis, Laboratoire LIP2, 2092, Tunis, Tunisie Email: habibsmei@gmail.com Advances in Science, Technology and Engineering Systems Journal Vol. 2, No. 6, 40-48 (2017)

Fault-Tolerant in Embedded Systems (MPSoC): Performance Estimation and Dynamic Migration Task

A R T I C L E I N F O A B S T R A C T Article history: Received: 09 April, 2017 Accepted: 24 June, 2017 Online: 20 July, 2017 Multiprocessor Systems-on-Chip (MPSoC) allow the implementation of heterogeneous architectures with a high integration capacity. In recent years, computational requirements MPSoC are increasing exponentially. This complexity, coupled with constantly evolving specifications, has forced designers to consider intrinsically flexible implementations. Deploying applications typical of multimedia domains is difficult, not only due to the heterogeneous parallelism in the platforms, but also due to the performance constraints that typify these systems. An application can be modeled as a set of cooperative tasks. A task can be implemented in software or in hardware depending on its complexity and the involved cost. Our proposal is a fault tolerance approach which combines the results of a performance model and a technical’s fault tolerance. We interest of the dynamic migration task to resolve the Fault-Tolerant for Multiprocessors Embedded System. We exploited an example of multimedia application (MJPEG decoder) to find optimal Fault tolerance systems. Our aim in this paper is to exploit the classic technique of fault tolerance. The solution chosen is the transformation of software processing into hardware processing. And also, exploitation of hybrid models (simulation/analytics). The goal is to have a Fault Tolerant Embedded System.

Pipelining the HEVC decoder on ZedBoard plateform

For different applications like high quality Internet video, mobile video or digital TV, efficient coding of video signals is required to meet technical constraints as bandwidth, latency or execution time. To cope with these constraints and the growing demand in terms of resolution and quality as HD, Quad-HD and UHD videos, more efficient coding is required. For that, the h.265 HEVC (High Efficiency Video Coding) is developed by JCT-VC to substitute to MPEG-2, MPEG-4 and h.264 codecs.

Automatic generation of software-hardware migration in MPSoC systems

we are going to focus on the study and the design of MPSOC systems, more precisely as part of improving the performances of the applications implanted on MPSOC architecture. The objective of this research is to study the problems of the passage from a purely software realization to a realization admitting one or several hardware components and to elaborate a methodology of automatic generation of the migration of a software task into a hardware component in MPSOC systems. The fact of transforming a software task into a hardware task leads to many changes, so much of the hardware side (connection, requirement of an interruption controller, …), of the software side (a task at least, Inputs/Outputs(I/O), synchronization, …) and from an architectural point of view, notable aspects of memorization of data. Experimentation is made on the MJPEG decoder to illustrate the effectiveness of our tool of automatic generation of migration.

Performance modeling and estimation along an MPSoC flow

We present in this paper, a new approach of heterogeneous multiprocessors systems-on-chip architecture (MPSoC) co-design based on performance control. This approach is centered on the structuring of the models and the levels of abstraction. Four models are proposed permuting to establish the refinement and the control at the time of the passage by six levels of abstraction. An extension of Khanpsilas model, based on the addition of the relative annotations to the times of execution of the parallel threads and to the size of the data exchanged by these threads, is used. Experimentation is achieved, in this context, on the MJPEG decoder and the Virtex II Pro platform of Xilinx.