Imed Bennour

Transaction level modeling of an OSI-like layered NoC

The increasing of SoC complexity and the need of performance, encourage designers to implement network on chip rather than point to point connection or shared bus. NoC borrows many concepts to computer network and includes enough complexity to be transaction level modeled. But first, we must precise both system design flow and NoC characteristics to be modeled

Modeling SW to HW task migration for MPSOC performance analysis

Codesign choices of a system differ in terms of different hardware/software partitions, different types of architectural components, different communication architectures, etc. This paper presents an analytic method to estimate the gain on a system throughput when a software task is selected to be moved to hardware during the codesign process. The method is based on formal transformations of a Synchronous Data Flow Graph that models the application as well as its mapping to architecture. The proposed method is applied to the MJPEG decoder using the predictable MPSOC design tool SDF3 [2].

Hardware/Software Co-Verification: Models and Methods

An efficient hardware-software co-verification methodology is essential in the design of systems on boards (SOB) and systems on chips (SOC). The increasing complexity of hardware and software makes the challenge of their integration more difficult than ever. This paper addresses the correctness verification of mixed hardware-software systems prior to IC fabrication. It presents the requirements of an efficient verification methodology, the multilevel co-verification approach, and a wide set of co-verification models based on different techniques like co-simulation, in circuit emulation, and hardware emulation. For each model, we present its advantages, its restrictions, and its implementation techniques. Then we study the factors that drive the co-simulation performance and we show how to fairly estimate this performance for different configurations.

A scheduling approach for packet-switched on-chip networks

Performance constraints imposed on the on-Chip System (SoC) design require efficiency and predictability of inter-core communication part in system. This implies the Quality-of-Service (QoS) requirement assurance for the communication. The current work presents a novel approach that borrows three Real-Time Operating System (RTOS) scheduling algorithms and adapts them to Networks-on-Chip (NoCs). This technique is designed specifically for multimedia and safety-critical real-time applications to reduce contention problem in packet-switched networks and provides QoS guarantees in terms of throughput and end-to-end latency. An HDL implementation of a NoC architecture has been simulated to prove our concept.

Modeling of Transaction Level SystemC modules and transactional channels with Petri nets

Currently, Transaction Level Modeling (TLM) is being used in the industry to solve a variety of practical problems during the design and deployment of electronic systems. TLM and SystemC gain popularity partly due to their simulation capabilities. However, formal models associated to SystemC designs and TLM descriptions are less developed. This paper describes how to translate SystemC modules defined at transactional level to formal Petri Net models. These models offer help in understanding the behaviour of third party modules used in component-based system. This paper focuses mainly on the translation of blocking and non-blocking Interface Method Calls which are the basis of TLM.

FJS Problem Under Machine Breakdowns

One of the most challenging problems in manufacturing field is to solve the flexible job shop (FJS) problem subject to machines breakdown. In this paper, we propose two rescheduling solutions to handle machine breakdowns: a PSO-based solution and a shifting-based solution. The first solution aims to improve the robustness while the second solution aims to improve the stability.

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

Chip communication architectures become an important element that is critical to control when designing a complex MultiProcessor System-on-Chip (MPSoC). This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism. Field-Programmable Gate Arrays (FPGA) has some perceived challenges. Overcoming those challenges with the right prototyping solutions is easy and cost-effective leading to much faster time-to-market. In this paper, we present an FPGA based on rapid prototyping in hardware/software co-design and design evaluation of a mixed HW/SW MPSoC using a NoC. A case study of two-dimensional mesh NoC-based MPSoC architecture is presented with a validation environment. The synthesis and implementation results of the NoC-based MPSoC on a Virtex 5 ML 507 enable a reasonable frequency (151.5 MHz) and a resource usage rate equals to 58% (6,586 out of 11,200 slices used).

TLM-2 base protocol analysis for model-driven design

The SoC design cost is not only dependent on implementation and manufacturing techniques, but also on the used methodologies and design tools. Transaction level modelling (TLM) is among the most promising electronic system level (ESL) design methodology. Recently, TLM-2 library places de facto SystemC as a standard when writing transaction level (TL) models. A TLM-2 based models and especially those using approximately-timed time coding style are very challenging to develop. In this paper, we expose techniques to write well-structured and modular TL models. These techniques bring up more elaborated semantics useful to automate model generation in the context of model-driven design methodology.

Improving the runtime of the serial PSO for the flexible job shop problem

The flexible job shop problem (FJSP) is a generalization of the classical job shop scheduling problem. The meta-heuristic particles swarm optimization (PSO) is well suited to solve the FJSP but it might be time consuming specially on monocore platforms. In this paper, we propose some PSO-FJSP variants that aim to improve the performance in term of CPU time.

Stepwise SystemC/TLM-2 models structuring and optimizations

Transaction level modelling (TLM) is among the most promising electronic system level (ESL) methodologies to handle the growing complexity of ESL designs. The last SystemC standard incorporates TLM concepts by adding the TLM-2 library. It places de facto SystemC and TLM-2 library as a standard when writing transaction level (TL) models. Standard establishment is a corner stone to pass to next logical steps that are transaction-level synthesis and electronic design automation. Nevertheless, good practice in writing and simulating systems at transaction level must be adopted to bring up more elaborated semantics of each TL model. We write this paper in this sense. Through guideline example, we expose techniques to write well-structured and modular TL models that help to explore and optimize the system architecture.