Kamyar Keikhosravy

A 0.13-

In this paper, a bulk-modulation technique is introduced for improving the performance of low-drop-out (LDO) voltage regulators. Compared to conventional LDO voltage regulators, the proposed circuit achieves improved accuracy, stability, and output load current capability. The technique is particularly suited for low-power applications such as biomedical implants and portable devices. A proof-of-concept prototype is designed and fabricated in 0.13-μm CMOS, to illustrate the enhancement that can be achieved by applying this technique. The proposed enhanced LDO regulator which is based on conventional LDO regulators is able to delivers up to 5 mA of load current while providing a 1 V (~ 1.5% load regulation) drawing 99.0 μA from a 1.2 V supply. Measurement results confirm that as compared to conventional LDOs, the proposed circuit offers better stability as well as %75 improvement in the load current delivery and ~10× faster recovery time for no-load to and from full-load transitions.

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A high-efficiency CMOS rectifier with low start-up voltage for ultra-high-frequency (UHF) radio-frequency identification (RFID) applications is presented. To enhance the power conversion efficiency (PCE) of the conventional rectifier when the input voltage (power) is low, appropriate gate-drive voltages for each stage of the rectifier are generated using a chain of auxiliary floating rectifier cells. Floating rectifier cells are optimized to generate shifted versions of the intermediate voltage of each stage to boost the drive voltage of NMOS and PMOS switching transistors and accordingly improve the PCE. The proposed rectifier architecture is designed in a standard 0.13μm CMOS technology. For a 950 MHz RF input and 50 kΩ output load, simulation results show that the rectifier achieves a PCE of 54% for a small input signal with an amplitude of 200 mV (-19 dBm) which is well below the nominal standard threshold voltage of MOS transistors in the technology used.

CMOS Low-Power Capacitor-Less LDO Regulator Using Bulk-Modulation Technique

A high-sensitivity fully passive 868-MHz wake-up radio (WUR) front-end for wireless sensor network nodes is presented. The front-end does not have an external power source and extracts the entire energy from the radio-frequency (RF) signal received at the antenna. A high-efficiency differential RF-to-DC converter rectifies the incident RF signal and drives the circuit blocks including a low-power comparator and reference generators; and at the same time detects the envelope of the on-off keying (OOK) wake-up signal. The front-end is designed and simulated 0.13μm CMOS and achieves a sensitivity of -33 dBm for a 100 kbps wake-up signal.

An efficiency enhancement technique for CMOS rectifiers with low start-up voltage for UHF RFID tags

In angioplasty with stent placement, re-narrowing of the artery within the stent site may occur due to the bodys natural response to “heal” the stented area. This re-narrowing, also known as “in-stent restenosis”, usually occurs within 6 months after surgery. To monitor and diagnose in-stent restenosis, passive telemonitoring using smart stents has been already proposed. In this paper, we present a feasibility study and advocate the use of an alternative method, namely active telemonitoring, which uses an integrated circuit embedded on the smart stent. Electromagnetic simulations and in-vitro measurements are presented to find the suitable range of frequency to wirelessly transfer power to the active device embedded on the smart stent. Furthermore, the range of induced power levels are simulated and experimentally verified.

A high-sensitivity fully passive wake-up radio front-end for wireless sensor nodes

An ultra-low-power CMOS voltage-controlled ring oscillator (VCRO) for passive ultra-high-frequency (UHF) radio-frequency identification (RFID) tags is presented. The gates of the complementary CMOS transistors in pseudo-differential (PD) delay cells are biased through quasi-floating gate (QFG) technique. The boosted gate-drive voltage enables operation of the differential delay cells with supply voltages smaller than the minimum required overdrive voltage of the two stacked transistors and accordingly facilitates the oscillation at ultra-Iow-power regime. QFG biasing technique also offers an additional control knob to tune the output frequency of the ring oscillator. The proposed two-stage PD-VCRO is designed and laid-out in a standard 0.13-μm CMOS technology. A voltage level converter is also presented to interface the output of the proposed VCRO with the succeeding circuitry. The entire VCRO core occupies an area of 25 μm×20 μm For a supply voltage of as low as 140 mV, an output frequency of 4 MHz is achieved at 3.6 nW power consumption. Although the intended application for the proposed VCRO is passive RFID tags, the architecture can be used in other ultra-low-power applications.

On the use of smart stents for monitoring in-stent restenosis

A CMOS rectifier with a wide input signal range for radio-frequency identification (RFID) applications is presented. Using quasi-floating gate technique, a gate-biasing scheme is proposed to provide a relatively flat power conversion efficiency (PCE) curve for a wide input voltage (power) range. The proposed technique also enables an efficient operation for input voltage levels well below the standard threshold voltage of the MOS switching transistors. Appropriate bias voltages for different stages of the rectifier are generated through a chain of low-power bandgap reference generators which impose minimal power and area overhead. The proposed rectifier architecture is designed and laid out in a standard 0.13-μm CMOS technology. For a 2.4 GHz RF input frequency and 30 kΩ output load, post-layout simulation results of the circuit show that a maximum PCE of 66.7% is achieved for an input signal with an amplitude (power) of 0.45 V (-8 dBm). While a high PCE of 60% is achieved for input voltage (power) levels as low as 0.25 V (-15 dBm), PCE maintains above 60% for a wide input voltage (power) range from 0.25 V to 0.7 V (-15 dBm to -3 dBm).

An ultra-low-power CMOS voltage-controlled ring oscillator for passive RFID tags

In this paper, an ultra-low-power system for wireless monitoring of inductively coupled biomedical implants is presented. The system is fully integrated and composed of custom rectifier, alignment and monitoring circuits with enhanced performance. The proposed system is described in the context of a smart-stent system that monitors the re-narrowing of blood vessels at the smart-stent site. The building blocks of the system are designed and simulated in a 0.13-μm CMOS technology. Simulation results for the monitoring system show that the proposed rectifier provides 53% power conversion efficiency (PCE) for -10.36 dBm input power (in the alignment mode) and 62% PCE for -4.06 dBm input power (in the monitoring mode). The alignment unit is capable of operating by drawing a 12 μA from a supply voltage as low as 0.6 V and the monitoring circuit consumes as low as 176 μW.

A CMOS rectifier with an extended high-efficiency region of operation

In this paper, an ultra wideband analog voltage-mode buffer is presented which can drive a load impedance of 50 Ω. The presented feedback-based buffer uses a compound amplifier which is a parallel combination of a high-DC gain operational amplifier and a operation transconductance amplifier to achieve a high unity gain bandwidth. A proof-of-concept prototype is designed and fabricated in a 0.13 μm CMOS process. The simulation and measurement results of the proposed buffer are in good agreement. The prototype buffer circuit consumes 7.34 mW from a 1.3-V supply, while buffering a 2 GHz sinusoidal input signal with a 0.4 V peak-to-peak (Vpp) amplitude and driving an AC-coupled 50-Ω load.

An ultra-low-power monitoring system for inductively coupled biomedical implants

This paper presents a fully integrated monitoring system for diagnosing restenosis in coronary-artery stents. Power is transferred wirelessly to the 0.13-μm CMOS monitoring circuit that is embedded on the stent and reads and transmits the sensory data from the pressure sensors which are also embedded on the stent. An auxiliary circuit is introduced to facilitate the alignment of the external reader with the stent. The alignment circuit starts operating from a rectified supply of 500 mV drawing 8.3 μA from the harvested supply voltage. The main transmitter which sends the sensory data operates from a rectified supply voltage of 880 mV while drawing ≈178 μA. The monitoring system provides a sensitivity of 555 kHz/fF. In-vitro measurement results confirm the performance of the system.

A wideband unity-gain buffer in 0.13-μm CMOS

This paper presents a efficiency enhanced rectifier for wireless energy harvesting (WEH) systems. A prototype of the proposed technique is implemented with discrete components and a microcontroller. Measurement results verify the performance of the approach for small input levels which corresponds to a WEH system operating over a long range.