Joon-Sung Park

Secondary-Side LLC Resonant Controller IC With Dynamic PWM Dimming and Dual-Slope Clock Generator for LED Backlight Units

This paper presents a low-profile low-cost (LLC) resonant controller IC for LED backlight units fully operating at the secondary side. The integrated dimming circuitry is proposed to improve the dynamic current control characteristics and the LED current density for the brightness modulation of a large screen liquid crystal display. A dual-slope clock generator, including a soft start, is proposed in order to overcome the frequency error due to the undershoot found in conventional approaches. In addition, a new dead-time generator is proposed in order to implement an accurate dead time independent of the output frequency of the clock generator. Protection circuits, such as a under voltage lock out, thermal shut down, open LED detector, and shorted LED detector, have been implemented in order to improve the reliability of the controller IC. The chip is fabricated using 0.35 μm bipolar CMOS DMOS decimal technology; the die size is 2 mm × 2 mm. The frequency of the clock generator ranges from 50 to 500 kHz; the dead time ranges from 50 ns to 2.2 μs. The efficiency of the LED driving circuit is 91%. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply voltage.

A design of high efficiency class-E power amplifier for wireless power transfer system

In this paper, class-E power amplifier (PA) with automatic power control loop and load compensation circuit is presented. The transmitted power is controlled by adjusting the signal applied to the gate of the power control transistor. In addition, a parallel capacitor is also controlled to enhance the efficiency and compensate for the load variation. This chip is implemented in a 0.35 µm BCD technology, and provides the output power control range of 10–30.2 dBm. The maximum power efficiency of the power amplifier is 71.5 %.

High Efficiency Controller IC for LLC Resonant Converter in 0.35 ㎛ BCD

This paper presents a LLC resonant controller IC for secondary side control without external active devices to achieve low profile and low cost LED back light units. A gate driving transformer is adopted to isolate the primary side and the secondary side instead of an opto-coupler. A new integrated dimming circuitry is proposed to improve the dynamic current control characteristic and the current density of a LED for the brightness modulation of a large screen LCD. A dual-slope clock generator is proposed to overcome the frequency error due to the under shoot in conventional approaches. This chip is fabricated using 0.35 ㎛ BCD technology and the die size is 2×2 ㎟. The frequency range of the clock generator is from 50 ㎑ to 500 ㎑ and the range of the dead time is from 50 ㎱ to 2.2 ㎲. The efficiency of the LED driving circuit is 97 % and the current consumption is 40 ㎃ for a 100 ㎑ operation frequency from a 15 V supply voltage.

A 67.5 dB SFDR Full-CMOS VDSL2 CPE Transmitter and Receiver with Multi-Band Low-Pass Filter

This paper presents a full-CMOS transmitter and receiver for VDSL2 systems. The transmitter part consists of the low-pass filter, programmable gain amplifier (PGA) and 14-bit DAC. The receiver part consists of the low-pass filter, variable gain amplifier (VGA), and 13-bit ADC. The low pass filter and PGA are designed to support the variable data rate. The RC bank sharing architecture for the low pass filter has reduced the chip size significantly. And, the 80 Msps, high resolution DAC and ADC are integrated to guarantee the SNR. Also, the transmitter and receiver are designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. The chip is implemented in 0.25 ㎛ CMOS technology and the die area is 5 ㎜ × 5 ㎜. The spurious free dynamic range (SFDR) and SNR of the transmitter and receiver are 67.5 ㏈ and 41 ㏈, respectively. The power consumption of the transmitter and receiver are 160 ㎽ and 250 ㎽ from the supply voltage of 2.5 V, respectively.

A low power, wide range VCO with automatic amplitude calibration loop

This paper presents a low-power VCO with automatic amplitude control loop to compensate for the process, voltage and temperature variation. The settling time of the loop is less than 300 ns in the SS corner case. Adaptive body-biasing (ABB) technique is also adopted to minimize the power consumption by lowering the threshold voltage of transistors in the negative-Gm core. The power consumption is 350 µW and the phase noise at the 1 MHz offset is −117 dBc/Hz when the VCO frequency is 3.2 GHz.

Experimental and Numerical Study on the Airflows in Four Asymmetric Nasal Cavities Due to Deviated Nasal Septum

Although the prevalence of the deviated nasal septum (DNS) is high, the number of asymptomatic person with DNS is higher than that of symptomatic patients. Most of the patients complain nasal discomfort in narrow side. Usually clinical laboratory tests are performed at each side separately; therefore it is very difficult to evaluate the both nasal cavities simultaneously. The purpose of this study is to evaluate the difference in aerodynamic parameters with presence of nasal symptoms, using PIV and CFD methods in asymmetric nasal cavities due to DSN. Aerodynamic parameters, such as velocity, flow rate in both nasal cavities, wall pressure and wall shear stress were evaluated in 2 symptomatic and 2 asymptomatic patients with DSN. Surface-rendered bilateral nasal cavity models were created from CT scans and used for making clear models for investigation with PIV method and for numeric method. Flow rates in both nasal cavities were different in symptomatic patients with PIV method and CFD method. High wall shear stress was noted at the narrow side of the symptomatic patients. These parameters can be used for the evaluation of the patients with nasal discomfort with CFD method.