YoungGun Pu

A Design of a Wireless Power Receiving Unit With a High-Efficiency 6.78-MHz Active Rectifier Using Shared DLLs for Magnetic-Resonant A4 WP Applications

This paper presents a full-CMOS wireless power receiving unit (WPRU) with a high-efficiency 6.78-MHz active rectifier and a dc-dc converter for magnetic-resonant alliance for wireless power (A4WP) applications. The proposed high-efficiency active rectifier with delay-locked loop (DLL) is a highly efficient receiver circuit intended for use in resonant wireless charging applications with a resonant frequency of 6.78 MHz. Each MOSFET of the proposed rectifier is turned on and off based on the ac input voltage. The delay between the ac input current and the ac input voltage due to the delays of internal blocks such as voltage limiter, level shifter, gate driver, and comparator will cause the reverse leakage current, degrading the power efficiency. Thus, the proposed active rectifier adopts the DLL to compensate for the delay caused by internal blocks, which leads to the removal of reverse leakage current and the power efficiency maximization. Moreover, to maximize power efficiency, negative impedance circuit (NIC) is also adopted to minimize switching loss. In the case of dc-dc converter, phase-locked loop is adopted for the constant switching frequency in process, voltage, and temperature (PVT) variation to solve the efficiency reduction problem, especially by heat. This chip is implemented using 0.18 μm BCD technology with an active area of 3.5 mm × 3.5 mm. When the magnitude of the ac input voltage is 8.95 V, the maximum efficiencies of the proposed active rectifier and dc-dc converter are 91.5% and 92.7%, respectively. The range of ac input voltage is 3-20 V, and the efficiency of the WPRU is about 80.86%.

A Wide-Locking-Range Dual Injection-Locked Frequency Divider With an Automatic Frequency Calibration Loop in 65-nm CMOS

This brief presents a wide-locking-range injection-locked frequency divider (ILFD) that uses an automatic frequency calibration loop. The proposed ILFD uses the ring oscillator to provide the high division ratio with small chip area. A dual-injection scheme is proposed in order to achieve the wide locking range of the ILFD. The free-running frequency of the ILFD is automatically digitally calibrated to reflect the frequency of the injected signal from the voltage-controlled oscillator. To control the frequency of the ILFD, the load current is digitally tuned with 3-bit control signal. The ILFD is fabricated using 65-nm CMOS process, and by tuning the load current, it achieves the wide operation frequency range of 14.1-45.8 GHz. When the input signal of 30 GHz is injected, the locking range of the ILFD is 7.2 GHz, while the power consumption is 2.5 mW from a 1-V supply voltage.

A Highly Linear, Small-Area Analog Front End With Gain and Offset Compensation for Automotive Capacitive Pressure Sensors in 0.35- m CMOS

This paper presents a highly linear, small-area analog front end with gain and offset compensation for automotive capacitive pressure sensor. We propose a capacitance-tovoltage converter circuit that measures the capacitance value of the capacitive sensor with the high accuracy and linearity. In this paper, the linearity of the analog front end is guaranteed using full-analog gain and an offset calibration circuit. The proposed design is implemented using CMOS 0.35 μm technology with an active area of 1.94 mm x 1.94 mm. The full output range is from 0.5 to 4.5 V. The ratiometricity is within ±0.7% when the supply voltage is changed by ±10%. The power consumption is 25 mW from a 5 V supply. The output accuracy is within ±1% with respect to Process, Voltage, Temperature variations.

A Triple-Mode Wireless Power-Receiving Unit With 85.5% System Efficiency for A4WP, WPC, and PMA Applications

This paper presents the design of a triple-mode wireless power-receiving unit (TWPRU) for battery charger with high efficiency. The TWPRU is proposed based on Alliance for Wireless Power (A4WP), Wireless Power Consortium (WPC), and Power Matters Alliance (PMA) standards. An adaptive alignment gate controller technique is proposed in the triple-mode active rectifier to block the reverse leakage current and improve the power conversion efficiency (PCE). This technique can compensate for the delays in the gate control signals of the main switching mosfets at different operating frequencies for A4WP, WPC, and PMA. The dead time of a dc–dc converter is optimally determined depending on the voltage and the temperature variations by phase calibration circuit. This chip with an active area of 5.0 mm × 3.5 mm is implemented in 0.18-μm BCD technology. The maximum PCEs of the triple-mode active rectifier are 91.7% in the A4WP mode and 92.7% in the WPC/PMA mode, respectively. The maximum PCE of the dc–dc converter is 92.3% at a load current of 500 mA, while the system efficiencies of TWPRU at A4WP and WPC/PMA modes are about 84.5% and 85.5%, respectively.

High power efficiency, 8 V∼20 V input range DC-DC buck converter with phase-locked loop

This paper presents a DC-DC buck converter with Phase-Locked Loop (PLL) to generate the constant switching frequency regardless of Process, Voltage, Temperature (PVT) variations. When the input range is from 8 V to 20 V, the proposed DC-DC buck converter with PLL is implemented to have over 90% efficiency in heavy load current of 1.0 A. also to reduce the size of the external device while maintaining high efficiency, 2 MHz switching frequency and 2.2 μH inductance were used. The proposed DC-DC buck converter with PLL to generate constant frequency to compensate for the efficiency variation. As a result, the efficiency variation is less than 1%. This chip was fabricated using 0.18 μm BCD technology, and the area is 3.96 mm2. The maximum efficiency of proposed DC-DC buck converter with PLL is 92.53%.

A design of 10-bit, 10MS/s Pipelined ADC with Time-interleaved SAR

This paper presents a 10-bit, 10MS/s pipelined ADC with a time-interleaved SAR. Owing to the shared multiplying-DAC between the flash ADC and the multi-channel-SAR ADC, the total capacitance of the SAR ADC is decreased by 93.75%. The proposed ADC architecture can therefore provide a higher resolution than the conventional time-interleaved flash-SAR ADC. The proposed 10-bit, 10 MS/s ADC achieves a 9.318-bit ENOB and a figure-of-merit of 357.11 fJ/conversion-step. The ADC that consumes 2.28mW under a supply voltage of 1.2V was fabricated in 0.13m CMOS and occupies an area of only 0.21mm2.

Low power FSK transceiver using ADPLL with direct modulation and integrated SPDT for BLE application

This paper presents a low power FSK transceiver with ADPLL based on direct modulation and integrated SPDT switch for Bluetooth low energy application. To ensure that the proposed low power transceiver can operate at 1 Mbps data rate, FSK modulation is implemented using an all-digital phase locked-loop with direct modulation technique. The SPDT switch is integrated to share the antenna and matching network between the transmitter and receiver, thus minimizing the system cost by reducing external components. The transceiver is implemented using 1P6M 55-nm CMOS technology. The die area of the transceiver with DC-DC converter is 1.79 mm2. The power consumption of the transmitter and receiver are 6 and 5 mW, respectively, when the output power level of the transmitter is 0 dBm. The noise figure of Rx is up to 6.8 dB with respect to channel frequencies. The phase noise of the ADPLL is −84.7 and −118.9 dBc/Hz at 100 kHz and 1 MHz offset from 2.44 GHz, respectively.