Kaoru Hashimoto

IO interface for over 25Gbps operation with low power

Recent communication for cloud computing strongly requires one order magnitude wider bandwidth than current one, such as over 28Gbps in SerDes and Interlaken protocols. So the technology of IO transmitter and receiver becomes to one of key issues. In generally, those high bandwidth IO systems consume relative high power due to relate with fCV^2 by CMOS transistor and parasitic capacitances. Additional problem is that the transmitter needs to drive long wiring of mother board or plug-in board. Some adaptive equalizer and timing adjust circuits must be implemented in the IO circuit that subsequently requires power consumption. Our research has been aimed to save to quarter times power of current ones even in over 28Gbps band width operation. The key was for balanced concurrent design from chip design to board design and open termination circuit system. These will be mentioned here.

Transmission characteristics in GHz region at the conductive adhesive joints

Interconnection technology using conductive adhesives is generally used in place of solder interconnection. However, it is not clarified whether or not the conductive adhesive joints are adequate to high-speed signal transmission and power supply with large current, because there are not suitable methods for measuring and evaluating performance of the intended electrical function of an electronic system. In this study, to elucidate the feasibility of the conductive adhesive joint for high-speed signal transmission, transmission characteristics at the conductive adhesive joint were experimentally evaluated using a specially designed interconnection model which consists of a high-speed LSI, a BGA package, and a circuit board. In this model, there is eight conductive adhesive joints in daisy chain configuration, and the signal passes through repeatedly between the BGA package and the circuit board. Experimental results show that pulse signals can be transmitted without degradation at the pulse rate of 12 Gbps through eight conductive adhesive joints in daisy chain configuration, and that this joint has an ability to supply power in the condition of current switching rate, di/dt, of 24 mA/60 ps although the direct current resistance of the conductive adhesive joint is approximately 10 times higher than that of the conventional solder joints. This is considered to be probably caused by the compensation effect of capacitive coupling interference for higher DC resistance.

Development of low characteristic impedance transmission line for power supply

In order to realize power supply method with less current/voltage fluctuation, new wiring technology using power supply/ground paired transmission lines with low characteristic impedance (Zo) is propose, and its possibility is examined. This new technology is based on the concept of ldquometamaterialrdquo, and is expected that Zo of the transmission lines will decrease to less than several ohms by the coupling effect of the surface plasmon and magnon interaction with lines. It is found that the transmission lines covered with a metamaterial sheet exhibit lower Zo than that of lines with metal sheet. This result suggests the feasibility to reduce characteristic impedance to several ohms in the power supply/ground paired transmission lines for power supply method in high clock frequency.

Co-design importance for over 20Gbps I/O interface

To achieve high performance communication it is necessary to consider all the design parameters for the switching circuit, interconnection and power supply. As these parameters definitely affect each other for over 20Gbps. These must be included for their optimization. These parameters are driver on-resistance (drivability), characteristic impedance of all connection routs, dependent frequency load with termination condition, receiver sensitivity and input impedance of power source within 1/4 wave length. Synopsys HSPICE is used for the simulation of the I/O interfaces with actual measurement S-parameter and 65nm process node in the TSMC IPs. In our study, we concluded that the power source line should be low impedance transmission line even 1mm length as similar as 1/4 wavelengths.

Measurement of transmission lines in the GHz region

In the general GHz measurement method, characteristics of signal transmission lines have been obtained through high-speed connecters to high-speed coaxial cables. However, measured data often did not accurately reflect actual circuit performance. This study aims to show the effect of the connection methods over 10Gbps. Teflon-based micro-strip line 200mm in length was chosen for its improved transmission characteristics to extract a connection effect using four different connectors and a Cascade Microtech prober. Simulation is also supported according to the experimental data. The results of the experiment show that the de-embedded operation by a blank calibration must be done to eliminate the connector effect in all connection methods with data rates over 10Gbps. However arrangement of the blank calibration needs careful thought to design. In this study, a smarter blank calibration method was attempted with more exact de-embedding.

300MM wiring enabling 28Gbps transmission on LCP board (PALAP)

Recent cloud computing communication strongly requires an order of magnitude higher bandwidth. For example, the maximum rate prescribed for SerDes and Interlaken is 28Gbps. This trend can be observed in new enterprise servers or enterprise routers. Boards and cards for enterprise devices are often relatively large, e.g., 300mm × 500mm, with more than 60 layers. Fine pitch wiring of over 300mm length is therefore needed in each layer. We have developed an LCP board with 28Gbps bandwidth along with a 300mm wiring length, 100um width and 380um pitch, to be described in detail. The board can be produced using DENSOs PALAP process, which is useful for high-density solutions involving more than 100 layers.

High speed LCP board for 28Gbps transmission through 300mm

Recent cloud computing communication strongly requires an order of magnitude higher bandwidth. For example, the maximum rate prescribed for SerDes and Interlaken is 28Gbps. This trend can be observed in new enterprise servers or enterprise routers. Boards and cards for enterprise devices are often relatively large, e.g., 300mm × 500mm, with more than 60 layers. Fine pitch wiring of over 300mm length is therefore needed in each layer. We have developed an LCP board with 28Gbps bandwidth along with a 300mm wiring length,. The board can be produced using DENSOs PALAP process, which is useful for high-density solutions involving more than 100 layers.

Development of touch panel system by single layer without pattern: Capable large touch panel due to large S/N and simple structure

We propose a novel touch panel structure, sensing method, and system which composes a low-cost transparent electrically-conductive thin film with higher Rs than the ITO film by two orders of magnitude. Relatively small number of extraction electrodes is directly attached upon the thin film without any circuit pattern. The proposed panel can realize even the wall tapestry-type touch panel of larger area as well as the smaller size one, and also can play single and multi-touch operations even through gloved fingers. In this paper, we will mainly mention about this packaging technology.

Power/ground wiring for high speed driver: Evaluating method by comparison with actual and simulation schemes

In our previous studies [1], [2], good power supply wirings on a chip have provided excellent high-speed switching and tinny power swing fluctuation. In this study, we again confirmed this by higher precision re-measurements correlated with simulations. If the power integrity (PI) would be better on the circuit, the circuit would be expected that the CMOS driver makes it sure to take higher-speed switching. Such kind of scheme had not been tried previously, because the power line performance expression by SPICE tool had to be difficult to coincident with actual power line. We planed to build the power supply circuit model by SPICE tool reflected faithfully with the test coupon. As the simulation model from the transmission line for the power line is coincided with actual physical structure, we can make the concept how to design and produce circuits from the variation of simulation results. Then we can get the key design rule for over Gbps region on a input/output (I/O) interface circuit system.

Fundamental study of direct current resistance effect on transmission line characteristics

High-speed transmission line characteristics have been analyzed from the point view of many parameters effects in huge amount of papers. As far as maintaining geometric (dimensional) similarity of transmission line configurations, i.e., shrink or expansion of cross-sectional dimension, characteristics of transmission lines are not affected by their configurations based on electromagnetism from Maxwells equations. However, direct current resistance (DCR) and skin depth surface/bulk ratio (SBR) of metal conductor in constant transmission length are changed even if geometric similarity is maintained. There have been seen no previous studies performed from this stand point. Therefore, as a fundamental study we examined on characteristics of transmission lines with geometric similarity by focusing on the effect of DCR and SBR. Time domain reflectometry (TDR) profiles, clock pulse rise/fall times (tr/tf), and eye-patterns were measured on the transmission line samples with different dimensions (line width and thickness) while maintaining geometric similarity. Experimental results suggest that the surface electron behavior would be related with DCR and SBR on the characteristics of transmission lines despite experimental accuracy is still not enough. These phenomena should more care for recent printed circuit boards over 10 Gbps/pin preferably toward 20 Gbps/pin.