Kareem Madkour

Multi-selection method for physical design verification applications

In this paper we present a modular approach which combines model based verification, pattern matching and machine learning methods in order to achieve a high accuracy over computing time ratio. We utilize pattern recognition technique using a supervised machine learning system (as opposed to pattern matching) to classify the patterns either as failures (hotspots) or non-failures, and we use pattern matching to detect all the outlier misses and false detections in each of the regions (based on the calibration set), which will be added or removed from the set of hotspots later on. Doing so allows us to do two things: Reduce the number of patterns that need to be pattern matched since only the outliers of the machine learning system need to be considered and more importantly it allows us to add trained predictability to new configurations that were not in the training set but that can be interpolated from the system. The results indicate that indeed it is possible to successfully combine Machine learning with pattern matching methods in order to achieve better predictability of errors of previously unseen data, while being exact in the treatment of previously observed data. We also explore possible avenues to further speed up the computation of the layout characterization process by inserting a global density grid, and assess the impact of model quality and aliasing under real detection conditions.

The effect of calibration feature weighting on OPC optical and resist models : investigating the influence on model coefficients and on the overall model fitting

Performing model based optical proximity correction (MB-OPC) is an essential step in the production of advanced integrated circuits that are manufactured with optical lithography technology. The accuracy of these models depends highly on the experimental data used in the model development (model calibration) process. The calibration features are weighted relative to each other depending on many aspects, this weighting plays an important role in the accuracy of the developed models. In this paper, the effect of the feature weighting on OPC models is studied. Different weighting schemes are introduced and the effect on both the optical and resist models (specifically the resist model coefficients) is presented and compared. The effect of the weighting on the overall model fitting was also investigated.

Design of silicon hollow waveguide in-line polarizer using a photonic crystal concept

An in-line polarizer based on a hollow waveguide and a one-dimensional (1D) photonic crystal concept is proposed and analysed. The hollow guide is designed to be symmetric, to achieve maximum coupling with the fibre, while the polarization dependence is achieved through the use of a 1D photonic crystal composed of alternating layers of silicon and air. It has been found that four layers can achieve an extinction ratio of about 11 dB mm−1 with a propagation loss of 0.9 dB mm−1.

Layout regularity metric as a fast indicator of high variability circuits

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Layout regularity is one of the trending techniques suggested by design for manufacturability (DFM) to mitigate process variations effect. However, there is no study relating either lithography or electrical variations to layout regularity. In this paper, a novel method is presented to model electrical variations due to systematic lithographic variations. Then, geometrical-based layout regularity metric was derived; this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The metric results compared to the electrical variability model results show matching percentage that can reach 80%. Calculation of the metric takes only few minutes on 1 mm × 1 mm.

Improvements in post-OPC data constraints for enhanced process corrections

Current state-of-the-art OPC (optical proximity correction) for 2-dimensional features consists of optimized fragmentation followed by site simulation and subsequent iterations to adjust fragment locations and minimize edge placement error (EPE). Internal and external constraints have historically been available in production quality code to limit the movement of certain fragments, and this provides additional control for OPC. Values for these constraints are left to engineering judgment, and can be based on lithography process limitations, mask house process limitations, or mask house inspection limitations. Often times mask house inspection limitations are used to define these constraints. However, these inspection restrictions are generally more complex than the 2 degrees of freedom provided in existing standard OPC software. Ideally, the most accurate and robust OPC software would match the movement constraints to the defect inspection requirements, as this prevents over-constraining the OPC solution. This work demonstrates significantly improved 2-D OPC correction results based on matching movement constraints to inspection limitations. Improvements are demonstrated on a created array of 2D designs as well as critical level chip designs used in 45nm technology. Enhancements to OPC efficacy are proven for several types of features. Improvements in overall EPE (edge placement error) are demonstrated for several different types of structures, including mushroom type landing pads, iso crosses, and H-bar structures. Reductions in corner rounding are evident for several 2-dimensional structures, and are shown with dense print image simulations. Dense arrays (SRAM) processed with the new constraints receive better overall corrections and convergence. Furthermore, OPC and ORC (optical rules checking) simulations on full chip test sites with the advanced constraints have resulted in tighter EPE distributions, and overall improved printing to target.

Hotspot detection using machine learning

As technology nodes continue shrinking, lithography hotspot detection has become a challenging task in the design flow. In this work we present a hybrid technique using pattern matching and machine learning engines for hotspot detection. In the training phase, we propose sampling techniques to correct for the hotspot/non-hotspot imbalance to improve the accuracy of the trained Support Vector Machine (SVM) system. In the detection phase, we have combined topological clustering and a novel pattern encoding technique based on pattern regularity to enhance the predictability of the system. Using the ICCAD 2012 benchmark data, our approach shows an accuracy of 88% in detecting hotspots with hit-to-extra ratio of 0.12 which are better results compared to other published techniques using the same benchmark data.

Toward automated parasitic extraction of silicon photonics using layout physical verifications

A physical verification flow of the layout of silicon photonic circuits is suggested. Simple empirical models are developed to estimate the bend power loss and coupled power in photonic integrated circuits fabricated using SOI standard wafers. These models are utilized in physical verification flow of the circuit layout to verify reliable fabrication using any electronic design automation tool. The models are accurate compared with electromagnetic solvers. The models are closed form and circumvent the need to utilize any EM solver for the verification process. Hence, it dramatically reduces the time of the verification process.

Work smarter not harder: How to get more results with less modeling

In this paper we study the importance of accurate model-based simulation on characterization of the integrated circuit performance. We analyze device sensitivity to process variability and its impact on circuit timing. We show that only a small fraction of devices whose characteristics are significantly affected by process variability actually have correspondingly significant effect on the overall circuit performance. We suggest several ways to use this observation to improve robustness of circuits. We see that a significant fraction of devices is affected by the layout context and should be considered sensitive. However, and it is especially true in large designs, only a small fraction of these devices is critical for the circuit performance. Obviously, to make the design more robust we have to avoid devices which are both sensitive and critical

A novel algorithm for automatic arrays detection in a layout

Integrated circuits suffer from serious layout printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to help reducing these systematic sub-wavelength lithography variations. From CAD point of view, regular layouts can be treated as repeated patterns that are arranged in arrays. In most modern mask synthesis and verification tools, cell based hierarchical processing has been able to identify repeating cells by analyzing the design’s cell placement; however, there are some routing levels which are not inside the cell and yet they create an array-like structure because of the underlying topologies which could be exploited by detecting repeated patterns in layout thus reducing simulation run-time by simulating only the representing cells and then restore all the simulation results in their corresponding arrays. The challenge is to make the array detection and restoration of the results a very lightweight operation to fully realize the benefits of the approach. A novel methodology for detecting repeated patterns in a layout is proposed. The main idea is based on translating the layout patterns into string of symbols and construct a “Symbolic Layout”. By finding repetitions in the symbolic layout, repeated patterns in the drawn layout are detected. A flow for layout reduction based on arrays-detection followed by pattern-matching is discussed. Run time saving comes from doing all litho simulations on the base-patterns only. The pattern matching is then used to restore all the simulation results over the arrays. The proposed flow shows 1.4x to 2x run time enhancement over the regular litho simulation flow. An evaluation for the proposed flow in terms of coverage and run-time is drafted.

A weak pattern random creation and scoring method for lithography process tuning

As the IC technology node moves forward, critical dimension becomes smaller and smaller, which brings huge challenge to IC manufacturing. Lithography is one of the most important steps during the whole manufacturing process and litho hotspots become a big source of yield detractors. Thus tuning lithographic recipes to cover a big range of litho hotspots is very essential to yield enhancing. During early technology developing stage, foundries only have limited customer layout data for recipe tuning. So collecting enough patterns is significant for process optimization. After accumulating enough patterns, a general way to treat them is not precise and applicable. Instead, an approach to scoring these patterns could provide a priority and reference to address different patterns more effectively. For example, the weakest group of patterns could be applied the most limited specs to ensure process robustness. This paper presents a new method of creation of real design alike patterns of multiple layers based on design rules using Layout Schema Generator (LSG) utility and a pattern scoring flow using Litho-friendly Design (LFD) and Pattern Matching. Through LSG, plenty of new unknown patterns could be created for further exploration. Then, litho simulation through LFD and topological matches by using Pattern Matching is applied on the output patterns of LSG. Finally, lithographical severity, printability properties and topological distribution of every pattern are collected. After a statistical analysis of pattern data, every pattern is given a relative score representing the pattern’s yield detracting level. By sorting the output pattern score tables, weak patterns could be filtered out for further research and process tuning. This pattern generation and scoring flow is demonstrated on 28nm logic technology node. A weak pattern library is created and scored to help improve recipe coverage of litho hotspots and enhance the reliability of process.