Karl-Friedrich Becker

Embroidered Interconnections and Encapsulation for Electronics in Textiles for Wearable Electronics Applications

This document explains different approaches to integrating electronics in textiles. It discusses reliability standards and tests for electronics in textiles. Encapsulation technologies are evaluated concerning their applicability in textile integrated electronics. Furthermore a specific assembly with embroidered wiring and embroidered interconnections has been developed and improved. Two different encapsulation technologies have been developed for this assembly. Standardized tests have been carried out to assess the reliability of the assembly and its encapsulations. Finally the achievements are critically discussed.

A low cost approach to CSP based on meniscus bumping, laser bonding through flex and laser solder ball placement

The drive toward larger die size with high I/O counts together with manufacturer demand for small, lightweight, reliable and low cost devices is a challenge for packaging technologies. Chip size/scale packages (CSPs) were designed to meet these demands without the drawbacks of direct chip attach (DCA). The techniques presented until now allow complete package testing, thereby solving the known good die issue and can easily cope with changing die size and I/O design. In future, the customer will expect to receive a tested package with standardized I/O layout. However, manufacturing costs are still too high. This paper presents an approach in which standard low cost materials are used, the number of process steps is reduced and new bumping and bonding technologies are used in order to lower overall system costs. The CSP described, the flexPAC, is based on interconnection of the bare IC to a single metal layer flexible interposer using the fiber push connection (FPC) principle. The solder for this assembly is applied to a wafer with electroless Ni metallization using a new low cost bumping approach: meniscus soldering. Mechanical stability is incorporated by using a low stress, low viscosity adhesive dispensed between chip and substrate prior to assembly. Finally, the CSP is bumped on the backside using a highly flexible high speed solder ball placement method. The package is fully surface mount compatible, allowing for a wide process window. One important issue is package reliability. The results of thermal cycling of the flexPAC, and repeated reflow and humidity tests are discussed here.

Packaging of Micro Devices for Automotive Applications - Techniques and Examples

Micro systems and micro devices play an important role in automotive applications. Today, sensors and actuators allow to increase safety, comfort and economy of modern cars. In order to facilitate the use of such fragile devices, packaging of these structures is on major issue. Due to the cost and yield issues associated with this process step, significant evolution on top of the microelectronic packaging techniques is required.

Trends in Fan-out wafer and panel level packaging

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. Besides developments to higher and heterogeneous integration the movement to larger formats and panel level packaging to lower cost is noticeable.

Inline Monitoring of Epoxy Molding Compound in Transfer Molding Process for Smart Power Modules

The quality of smart power modules strongly depends on the material characteristics of epoxy molding compound (EMC) and transfer molding process parameters. In order to predict the quality and to diminish the failure mechanisms, inline monitoring techniques in transfer molding process are essential. This work examines the inline identification of the variations in the EMC characteristics in the transfer molding process. Dielectric Analysis (DEA) is chosen as an inline technique and the influence of prolonged storage duration, moisture content and batch-to-batch variation on the characteristics of EMC are studied. In addition, the impact of molding temperature on the cure behavior of the EMC is in-situ examined. DEA results are verified and compared with the rheological and calorimetric analysis and good correlation is established.

New processes and materials for semiconductor components

To date, public interest in the development of new electronic systems has been primarily focused on advances in semiconductor technology and microsystem technology. However, in coming years, attention will shift to approaches that flexibly, cost-effectively and reliably integrate semiconductors into a miniature system. In this article, the Fraunhofer Institutes for Reliability and Microintegration (IZM) discuss this trend, also known as heterointegration, which will require new manufacturing processes and materials.

Neue Verfahren und Werkstoffe für Halbleiterkomponenten

Bislang standen bei der Realisierung neuer elektronischer Systeme die Fortschritte im Bereich der Halbleitertechnologie oder Mikrosystemtechnik im Mittelpunkt des Interesses. In Zukunft werden hingegen Ansatze fokussiert, die Halbleiterkomponenten flexibel, kostengunstig und zuverlassig zu einem miniaturisierten System zusammenfassen konnen. Das Fraunhofer-Institut fur Zuverlassigkeit und Mikrointegration (IZM) beschreibt diesen, auch Heterointegration genannten Trend, der durch neue Fertigungsverfahren und Werkstoffe erst ermoglicht wird.

Overmolded FC-SiP for Miniaturized Devices

The degree of integration of modern circuits has gone from singledie towards multi-die or even system partition integration. System-In-Package concepts allow to integrate in a hybrid form circuit components steming from different manufacturing processes e.g. CMOS, GaAs, MEMS as well as SMD chips. Combining Flip Chip technology, advanced PCB manufacturing, advanced assembly processes and large area overmolding, highly integrated and reliable sub-systems can be created. The paper describes the individual process steps for a GSM-Power Amplifier module, integrating the PA as a flip chip with the matching SMD components into a novel QFN concept featuring a laser structured bump-on-pad interconnect technology. Large area overmolding covers and protects the entire subsystem thus created. Manufacturing issues as well as specific fabrication details are highlighted and a reliability test shows the performance of the concept under harsh environmental load.