Karl Kragler

Directly sputtered stress-compensated carbon protective layer for silicon stencil masks

Silicon stencil masks for ion beam projection lithography have a protective layer stopping the ions and thus preventing a change in the Si membrane stress. This is needed to maintain extremely tight pattern placement specifications even when they are irradiated with high exposure doses. The fabrication of carbon protective layers by indirect sputter coating which are suitable for helium ion beam exposure has already been reported. This article describes a method of forming very low stress carbon protective layers based on direct radio frequency sputter coating with nitrogen added to the argon sputter gas and in situ thermal treatment using commercially available equipment. The carbon layers thus produced are stable in conventional environments. The article deals also with the physical characterization of carbon layers and the protection performances of these coatings under helium ion beam exposure using accelerated lifetime testing.

PN and SOI wafer flow process for stencil mask fabrication

Two process flows for the fabrication of stencil masks have been developed. The PN Wafer Flow- and the SOI Wafer Flow Process. Membranes and stencil masks out of different 6 inch Si base wafers with 3 micrometers membrane thickness and a membrane diameter between 120 mm and 126 mm were fabricated. The membrane stress depending on the material property and doping level has been determined. First metrology measurements have been carried out.

Stencil mask technology for ion beam lithography

Ion beam lithography is one of the most promising future lithography technologies. A helium or hydrogen ion beam illuminates a stencil membrane mask and projects the image with 4X reduction to the wafer. The development of stencil masks is considered to be critical for the success of the new technology. Since 1997, within the European Ion Projection Lithography MEDEA (Microelectronic Devices for European Applications) project silicon stencil masks based on a wafer- flow process are developed. They are produced in a conventional wafer line. Six inch SOI (silicon-on-insulator) wafers are patterned with an e-beam wafer writing tool, then trenches are etched by plasma etching. Afterwards, the membrane is etched by wet etch using the SOI-oxide layer as an etch stop. The last step is to add a coating layer, which is sputtered onto the membrane. It protects the mask against ion irradiation damage. For metrology and inspection, methods used for conventional chromium masks as well as new techniques are investigated. Results from placement measurements on the Leica LMS IPRO tool will be presented. Finally, methods for CD measurement, defect inspection, repair and in-situ-cleaning in the stepper will be discussed, including experimental information of first tests.

High precision stress measurement of ion projection lithography mask membranes

In this article, we describe an instrument for measuring the mean stress of large-area membranes for ion projection lithography (IPL) stencil masks. The apparatus incorporates two improvements over the conventional bulge technique, where the deflection at the center of a membrane is measured as a function of differential pressure across it, that provide a hundred-fold improvement in the precision of the measurement. The first is to simply place the membrane, without an o-ring or mechanical clamp, on an optically flat silicon ring separating the two pressure chambers. This eliminates the in-plane mounting forces that previously resulted in 1–2 MPa errors. The close contact between the integral ring supporting the mask and the silicon ring provides an adequate vacuum seal between the chambers. The second improvement is to provide an isothermal environment to reduce stress errors due to temperature variations in the membrane. As a result, the measured stress is independent of temperature and the standard deviation (1σ) of measured stress is 0.02 MPa.