Richard Simpson

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of <10-15 is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and 0.45mm2 per TX/RX pair

The Texas Instruments 34010 Graphics System Processor

The 34010 Graphics System Processor is a 32-bit graphics microprocessor capable of executing high-level languages. It combines a full general-purpose instruction set with a powerful set of graphics instructions that includes arithmetic as well as Boolean pixbits (pixel block transfers). Because it is completely programmable, the 34010 can be used in many different graphics and nongraphics applications. it was designed to support a wide range of display resolutions and pixel sizes, as well as applications such as page (laser) printers, ink jet printers, data compression, and facsimile transmission. The 34010 includes such system features as an on-board instruction cache, full interrupt capability, wait and hold functions, and display timing control, as well as test and emulation support. Unique among todays microprocessors, the 34010 addresses all memory down to the bit level with variably sized fields rather than the common byte or word addressing. For example, the 34010 can push a 5-bit quantity onto a stack. This field-processing capability is an integral part of the basic architecture.

Circular bist testing the digital logic within a high speed serdes

High Speed Serializer Deserializers (serdes) are traditionally tested using functional BIST. This paper presents an improved BlST for testing the digital part of a serdes using circular BET.