Karl-Magnus Persson

Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.

In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.

A High-Frequency Transconductance Method for Characterization of High-

A novel method that reveals the spatial distribution of border traps in III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. The increase in transconductance with frequency is explored in a very wide frequency range (1 Hz-70 GHz) and a distributed RC network is used to model the oxide and trap capacitances. An evaluation of vertical InAs nanowire MOSFETs and surface-channel InGaAs MOSFETs with Al₂O₃/HfO₂ high-κ gate dielectric shows a deep border-trap density of about 10²⁰cm^-3eV^-1 and a near-interfacial trap density of about 10²¹cm^-3eV^-1. The latter causes an almost steplike increase in transconductance at 1-10 GHz. This demonstrates the importance of high-frequency characterization of high-κ dielectrics in III-V MOSFETs.

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This paper presents dc and RF characterization as well as modeling of vertical InAs nanowire (NW) MOSFETs with L_G=200 nm and Al₂O₃/HfO₂ high-κ dielectric. Measurements at V_DS=0.5 V show that high transconductance (g_m=1.37 mS/μm), high drive current (I_DS=1.34 mA/μm), and low ON-resistance (R_ON=287 Ωμm) can be realized using vertical InAs NWs on Si substrates. By measuring the 1/f-noise, the gate area normalized gate voltage noise spectral density, S_VG·L_G·W_G, is determined to be lowered by one order of magnitude compared with similar devices with a high-κ film consisting of HfO₂ only. In addition, with a virtual source model we are able to determine the intrinsic transport properties. These devices (L_G=200 nm) show a high injection velocity (v_inj=1.7×10⁷ cm/s) with a performance degradation for array FETs predominantly due to an increase in series resistance.

Border Traps in III-V MOSFETs

This letter presents dc characteristics and low-frequency noise (LFN) measurements on single vertical InAs nanowire MOSFETs with 35-nm gate length and HfO₂ high-¿ dielectric. The average normalized transconductance for three devices is 0.16 S/mm, with a subthreshold slope of 130 mV/decade. At 10 Hz, the normalized noise power <i>SI</i> /<i>Id</i> ² measures 7.3 × 10^-7 Hz^-1. Moreover, the material-dependent Hooges parameter at room temperature is estimated to be 4.2 × 10^-3.

Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates

In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on- and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.

Low-Frequency Noise in Vertical InAs Nanowire FETs

By measuring 1/f-noise in wrap-gated InAs nanowire metal-oxide-semiconductor field-effect transistors with transport dominating, controllably, in either an inner, core channel, or an outer, surface ...

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

We have developed a self-aligned L_g = 55 nm In_0.53Ga_0.47As MOSFET incorporating metal-organic chemical vapor deposition regrown n⁺⁺ In_0.53Ga_0.47As source and drain regions, which enables a record low on-resistance of 199 Ωμm. The regrowth process includes an InP support layer, which is later removed selectively to the n⁺⁺ contact layer. This process forms a high-frequency compatible device using a low-complexity fabrication scheme. We report on high-frequency measurements showing f_max of 292 GHz and f_t of 244 GHz. These results are accompanied by modeling of the device, which accounts for the frequency response of gate oxide border traps and impact ionization phenomenon found in narrow band gap FETs. The device also shows a high drive current of 2.0 mA/μm and a high extrinsic transconductance of 1.9 mS/μm. These excellent properties are attributed to the use of a gate-last process, which does not include high temperature or dry-etch processes.

Surface and core contribution to 1/f-noise in InAs nanowire metal-oxide-semiconductor field-effect transistors

Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.

High-Frequency Performance of Self-Aligned Gate-Last Surface Channel MOSFET

We have developed a self-aligned L_g = 55 nm In_0.53Ga_0.47As MOSFET incorporating metal-organic chemical vapor deposition regrown n⁺⁺ In_0.53Ga_0.47As source and drain regions, which enables a record low on-resistance of 199 Ωμm. The regrowth process includes an InP support layer, which is later removed selectively to the n⁺⁺ contact layer. This process forms a high-frequency compatible device using a low-complexity fabrication scheme. We report on high-frequency measurements showing f_max of 292 GHz and f_t of 244 GHz. These results are accompanied by modeling of the device, which accounts for the frequency response of gate oxide border traps and impact ionization phenomenon found in narrow band gap FETs. The device also shows a high drive current of 2.0 mA/μm and a high extrinsic transconductance of 1.9 mS/μm. These excellent properties are attributed to the use of a gate-last process, which does not include high temperature or dry-etch processes.

Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

We report on RF characterization of vertical, 100-nm-gate length InAs nanowire MOSFETs, utilizing wrap-gate technology and Al<inf>2</inf>O<inf>3</inf> high-K gate oxide. The transistors show f<inf>t</inf>=5.6 GHz and f<inf>max</inf>=22 GHz, mainly limited by parasitic capacitances. The RF device performance is described using a hybrid-π model taking hole generation at the drain into account. Electrostatic modeling of the parasitic capacitances for arrays of vertical nanowires indicates that a strong reduction in extrinsic capacitances can be achieved for devices with a small inter-wire separation.