Claes Thelander

Vertical InAs Nanowire Wrap Gate Transistors on Si Substrates

We report on InAs enhancement-mode field-effect transistors integrated directly on Si substrates. The transistors consist of vertical InAs nanowires, grown on Si substrates without the use of metal seed particles, and they are processed with a 50-nm-long metal wrap gate and high-kappa gate dielectric. Device characteristics showing enhancement-mode operation are reported. The output characteristics are asymmetric due to the band alignment and band bending at the InAs/Si interface. The implemented transistor geometry can therefore also serve as a test structure for investigating the InAs/Si heterointerface. From temperature-dependent measurements, we deduce an activation energy of about 200 meV for the InAs/Si conduction band offset.

Electrical properties of InAs-based nanowires

Semiconductor nanowires are grown using chemical beam epitaxy and metal organic vapor phase epitaxy from size‐selected gold nanoparticles acting as catalysts. By changing materials during the growth it is possible to form heterostructures both along the length of the nanowires but also in a core‐shell fashion. In particular, incorporation of pairs of InP tunnel barriers in InAs nanowires has been used to fabricate single‐electron transistors and resonant tunneling diodes.