Harika Manem

Leveraging Memristive Systems in the Construction of Digital Logic Circuits

The recent emergence of the memristor has led to a great deal of research into the potential uses of the devices. Specifically, the innate reconfigurability of memristors can be exploited for applications ranging from multilevel memory, programmable logic, and neuromorphic computing, to name a few. In this work, memristors are explored for their potential use in dense programmable logic circuits. While much of the work is focused on Boolean logic, nontraditional styles including threshold logic and neuromorhpic computing are also considered. In addition to an analysis of the circuits themselves, computer-aided design (CAD) flows are presented which have been used to map digital logic functionality to dense complementary metal-oxide-semiconductor (CMOS)-memristive logic arrays. As exemplified through the circuits described here memristor-based digital logic holds great potential for high-density and energy-efficient computing.

An Energy-Efficient Memristive Threshold Logic Circuit

Researchers have claimed that the memristor, the fourth fundamental circuit element, can be used for computing. In this work, we utilize memristors as weights in the realization of low-power Field Programmable Gate Arrays (FPGAs) using threshold logic which is necessary not only for low power embedded systems, but also realizing biological applications using threshold logic. Boolean functions, which are subsets of threshold functions, can be implemented using the proposed Memristive Threshold Logic (MTL) gate, whose functionality can be configured by changing the weights (memristance). A CAD framework is also developed to map the weights of a threshold gate to corresponding memristance values and synthesize logic circuits using MTL gates. Performance of the MTL gates at the circuit and logic levels is also evaluated using this CAD framework using ISCAS-85 combinational benchmarking circuits. This work also provides solutions based on device options and refreshing memristance, against drift in memristance, which can be a potential problem during operation. Comparisons with the existing CMOS look-up-table (LUT) and capacitor threshold logic (CTL) gates show that MTL gates exhibit less energy-delay product by at least 90 percent.

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory

With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed thus far that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems. This work describes the design of such a multilevel memristor memory (MLMM) system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin (NM) for accurately reading the data stored in a device are analyzed.

Memristor based programmable threshold logic array

In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty.

Design Considerations for Multilevel CMOS/Nano Memristive Memory

With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems by facilitating the implementation of multilevel logic. This work describes the design of such a multilevel nonvolatile memristor memory system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin for accurately reading and writing the data stored in a device are analyzed. Also analyzed are the nondisruptive read and write methodologies for the hybrid multilevel memristor memory to program and read the memristive information without corrupting it. This work showcases two write methodologies that leverage the best traits of memristors when used in either linear (low power) or nonlinear drift (fast speeds) modes. The system can therefore be tailored depending on the required performance parameters of a given application for a fast memory or a slower but very energy-efficient system. We propose for the first time, a hybrid memory that aims to incorporate the area advantage provided by the utilization of multilevel logic and nanoscale memristive devices in conjunction with CMOS for the realization of a high density nonvolatile multilevel memory.

A read-monitored write circuit for 1T1M multi-level memristor memories

Technology migration into nano and molecular scales has led to the design of several hybrid CMOS/nano logic and memory architectures that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale memory and logic systems by facilitating the implementation of multi-level logic. In this work we propose a sneak-path free memory architecture, the 1T1M (1 transistor per memristor) that provides for 2-bit storage in each data cell (memristor). Robust read and write methodologies for the proposed architecture are also discussed and tradeoffs between faster write speeds and larger read noise margins are also analyzed. Another highlight of this work is the usage of the exponential drift memristor model to further enhance write speeds of these devices which are otherwise much slower.

Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array

Neuromorphic computing is an attractive avenue of research for processing and learning complex real-world data. With technology migration into nano and molecular scales several area and power efficient approaches to the design and implementation of artificial neural networks have been proposed. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems by facilitating the implementation of multilevel logic. Specifically, the innate reconfigurability of memristors can be exploited to realize synapses in artificial neural networks. This work focuses on the development of a variation-tolerant training methodology to efficiently reconfigure memristive synapses in a Trainable Threshold Gate Array (TTGA) system. The training process is inspired from the gradient descent machine learning algorithm commonly used to train artificial threshold neural networks, perceptrons. The design and CMOS/Nano implementation of the TTGA system from trainable perceptron based threshold gates is detailed and results are provided to showcase the training process and performance characteristics of the proposed system. Also shown are the results for training a 1T1M (1 Transistor and 1 Memristor) multilevel memristive memory and its performance characteristics.

A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays

Recent research into molecular scale electronics has led to the realization of novel nanoscale devices that can be used to implement circuits such as what we dub Programmable Majority Logic Arrays (PMLA). A PMLA leverages two characteristics found in molecular electronic devices, hysteretic switching and negative differential resistance (NDR), in the implementation of a PLA based on majority logic. This paper deals with the integration of several nanoscale PMLA units with micro scale technologies to implement a high density FPGA architecture. One of the key contributions of this work is the interface between the top nanoscale layer and a lower CMOS layer. Two approaches are considered for interfacing these two technologies: (1) direct connection and (2) connection utilizing tapered buffers between the layers for improved delay. The intermediate tapered buffers in the second approach ensure that the variation in feature size, and hence load capacitance, from one layer to the next is not too substantial. This paper also demonstrates the potential of the PMLA FPGA from a high level perspective in terms of increased density and performance for a set of applications.

Techniques for Improved Reliability in Memristive Crossbar PUF Circuits

Hardware security has emerged as an important field of study aimed at mitigating issues such as integrated circuit (IC) piracy and counterfeiting. One popular solution for such hardware security attacks are physically unclonable functions (PUF) which provide a hardware specific unique identification based on intrinsic process variations within individual integrated circuit implementations. At the same time, as technology scaling progresses further into the nanometer region, emerging nanoelectronic technologies such as memristors become viable options. Several examples of nanoelectronic memristor-based PUF circuits have been proposed in the last few years. In this paper, we analyze the behavior of crossbar memristive PUF circuits under different environmental conditions such as varying temperature, supply rail voltage fluctuations and aging. We also present an approach that improves the reliability of these circuits, taking environmental variations into consideration. The advantages and challenges associated with these PUFs are also discussed in detail. Specifically, we show results for security metrics including reliability, uniqueness and uniformity. These security performance results are presented alongside estimates for power, area and delay showing the advantages of using nanoelectronic PUFs from the perspective of efficient resource utilization.

An extendable multi-purpose 3D neuromorphic fabric using nanoscale memristors

Neuromorphic computing offers an attractive means for processing and learning complex real-world data. With the emergence of the memristor, the physical realization of cost-effective artificial neural networks is becoming viable, due to reduced area and increased performance metrics than strictly CMOS implementations. In the work presented here, memristors are utilized as synapses in the realization of a multi-purpose heterogeneous 3D neuromorphic fabric. This paper details our in-house memristor and 3D technologies in the design of a fabric that can perform real-world signal processing (i.e., image/video etc.) as well as everyday Boolean logic applications. The applicability of this fabric is therefore diverse with applications ranging from general-purpose and high performance logic computing to power-conservative image detection for mobile and defense applications. The proposed system is an area-effective heterogeneous 3D integration of memristive neural networks, that consumes significantly less power and allows for high speeds (3D ultra-high bandwidth connectivity) in comparison to a purely CMOS 2D implementation. Images and results provided will illustrate our state of the art 3D and memristor technology capabilities for the realization of the proposed 3D memristive neural fabric. Simulation results also show the results for mapping Boolean logic functions and images onto perceptron based neural networks. Results demonstrate the proof of concept of this system, which is the first step in the physical realization of the multi-purpose heterogeneous 3D memristive neuromorphic fabric.