Karthik Rajagopal

A high performance, high voltage output buffer in a low voltage CMOS process

The proposed output buffer circuit uses 1.8V transistors in 90nm CMOS process to develop I/Os for 2.5V and 3.3V interfaces. A voltage clamp circuit, bias generators, and a feedback circuit are used to ensure reliability and noise decoupling. Use of these circuits enables achieving low power (130/spl mu/A) and high performance (up to 275MHz) in a comparative area of an equivalent I/O in 90nm 3.3V process.

Novel low delay slew rate control I/Os

As technology is shrinking to sub 100nm, the sensitivity of circuits towards Process, Temperature, Voltage (PTV) and load variations is limiting circuit performance and yield [1–3]. For example in the specific case of IOs, it is difficult to meet various specifications like the rise and fall times, current drive strength, jitter, power and ground bounce across the wide range of I/O operating condition. Driver circuits are oversized to meet performance goals at slow corners. However, this leads to high current and Simultaneous Switching Noise (SSN) at fast corners. [1]. Further, high output edge switching rates lead to EMI issues [4]. In this paper, we propose a technique which can address the EMI and noise concerns without compromising the I/O performance. Our results show that the proposed scheme offers advantage over various PTV compensation schemes which do not target load compensation. The proposed scheme also offers advantage over the traditional slew rate control schemes which target PTV as well as load compensation but require a performance - noise tradeoff.

An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process

The aggressive scaling of CMOS process is central to the continued performance enhancement of microprocessors. While the process scales every generation the I/O interface standards do not change at the same rate. This introduces a host of reliability issues. One not only needs to design for performance, but should also meet the reliability goals in the scaled technology for these standards. This paper presents a 3.3V I/O buffer designed using 1.8V transistors in a 65nm bulk CMOS process. Proposed I/O uses a novel differential amplifier based pre-driver topology, which has excellent gate-oxide reliability, runs at 200MHz and has comparative area and static power of an equivalent I/O in 65nm 3.3V CMOS process.

Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process

Integration of legacy interfaces demand need for 3.3V I/Os in modern day SOCs. Low cost solutions exists by build 3.3V I/Os using specially biased 1.8V transistors imposing a serious limitation of trade-off between power, performance and reliability. This paper presents an I/O built using a dynamically biased differential amplifier based pre-driver circuit, with which excellent performance has been achieved up to 200MHz along with up to 30X reduction in power without compromise to reliability.