Rajat Chauhan

A Robust Level-Shifter Design for Adaptive Voltage Scaling

Voltage scaling is one of the knobs that is used today to control both static and the active power for SoCs. The SoC core supply voltage is scaled adaptively based on the performance needs. But it is also required to maintain the external electrical chip interface protocol, which may run at a different voltage level. The chip interfaces need to operate reliably under adaptively scaling core voltage and fixed 10 supply voltage. Within the 10 circuits, voltage level shifters are used to communicate between two voltage domains. This paper examines the performance of a conventional voltage level shifter and describes a novel high performance level shifter that is more robust under adapting voltage scaling.

A high performance, high voltage output buffer in a low voltage CMOS process

The proposed output buffer circuit uses 1.8V transistors in 90nm CMOS process to develop I/Os for 2.5V and 3.3V interfaces. A voltage clamp circuit, bias generators, and a feedback circuit are used to ensure reliability and noise decoupling. Use of these circuits enables achieving low power (130/spl mu/A) and high performance (up to 275MHz) in a comparative area of an equivalent I/O in 90nm 3.3V process.

Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system power

This paper explains a fail-safe I/O circuit to control the RESET# pin of DDR3 SDRAM to achieve ultra-low power system operation. Conventional Fail-safe I/O circuits withstand conditions like hot plug, hot-insertion, hot-swapping and ensure IC reliability by limiting the current flowing into the I/O pin. However they do not guarantee the functionality during supply-ramp cycles where the I/O supply is turned off while its output is pulled high externally. In case of RESET#, a small glitch on I/O pin can reset the DRAM chip. The fail-safe I/O circuit explained in this paper ensures smooth transition between ultra-low power suspension mode, where full chip supply is turned off, and normal operation mode.

Input Referred Offset Reduction in Very High Speed Differential Receivers

This paper explains a circuit architecture to minimize the impact of IRO (Input Referred Offset) in Differential amplifier based Receivers. Such receivers are used on high speed interfaces, like DDRs and LVDS, as they provide better timing and ensure proper detection of small swing signals. However the mismatch between the differential input arms causes IRO which in turn causes duty cycle distortion and degrades the receiver timing. At very high speeds it becomes necessary to minimize the impact of IRO. The proposed IRO reduction circuit uses a Digital controller which measures and reduces the IRO using a binary code. The timing improvement provided by this circuit scheme is validated on Silicon in 28nm CMOS process.