Vinod Menezes

A Robust Level-Shifter Design for Adaptive Voltage Scaling

Voltage scaling is one of the knobs that is used today to control both static and the active power for SoCs. The SoC core supply voltage is scaled adaptively based on the performance needs. But it is also required to maintain the external electrical chip interface protocol, which may run at a different voltage level. The chip interfaces need to operate reliably under adaptively scaling core voltage and fixed 10 supply voltage. Within the 10 circuits, voltage level shifters are used to communicate between two voltage domains. This paper examines the performance of a conventional voltage level shifter and describes a novel high performance level shifter that is more robust under adapting voltage scaling.

A high performance, high voltage output buffer in a low voltage CMOS process

The proposed output buffer circuit uses 1.8V transistors in 90nm CMOS process to develop I/Os for 2.5V and 3.3V interfaces. A voltage clamp circuit, bias generators, and a feedback circuit are used to ensure reliability and noise decoupling. Use of these circuits enables achieving low power (130/spl mu/A) and high performance (up to 275MHz) in a comparative area of an equivalent I/O in 90nm 3.3V process.

A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture

Ternary content addressable memory (TCAM) is used for high-speed table lookups. The dynamic power consumption of TCAMs is one of the main challenges for keeping up with high performance requirements. System level reliability is impacted by devices that produces large peak current demands on the power grid. This paper presents a TCAM compiler based on a static complementary TCAM bitcell for reduced dynamic power and reduced decoupling capacitance(dcap) requirement. The two stage architecture comprise of static TCAM cells with a match forward feature and then a static AND-tree structure. This TCAM compiler configurations have been implemented on 40nm CMOS technology testchip and experimental results demonstrate the performance upto 650Mhz and 0.5fJ/bit/search energy for a 512wordsx256bit macro.

An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process

The aggressive scaling of CMOS process is central to the continued performance enhancement of microprocessors. While the process scales every generation the I/O interface standards do not change at the same rate. This introduces a host of reliability issues. One not only needs to design for performance, but should also meet the reliability goals in the scaled technology for these standards. This paper presents a 3.3V I/O buffer designed using 1.8V transistors in a 65nm bulk CMOS process. Proposed I/O uses a novel differential amplifier based pre-driver topology, which has excellent gate-oxide reliability, runs at 200MHz and has comparative area and static power of an equivalent I/O in 65nm 3.3V CMOS process.

Design and technology interaction beyond 32nm

This paper will discuss the challenges that continued technology scaling present to circuit designers and how the close interaction between the development of technology, design automation (EDA) tools and the circuit designer can overcome these challenges and enable designs that deliver the benefits customers expect from continued technology scaling.

A low-power 333Mbps mobile-double data rate output driver with adaptive feedback to minimize overshoots and undershoots

An area-efficient, low power, low voltage mobile double-data rate output driver topology for mobile applications is proposed. The driver with its feedback architecture minimizes the overshoot and undershoots by over 50% as compared to a conventional driver. It automatically adapts to a wide range of transmission line impedance (Z0 of 40-70 ohms) and delay (Td of 10--180 ps) using adaptive feedback. It operates at 333Mbps across a wide load range and does not require a separate area and power expensive process-temperature-voltage (PTV) compensation circuit. The feedback compensates for PTV and load variations. It has a near zero stand-by power dissipation.

Optimization of 1.8V I/O circuits for performance, reliability at the 100 nm technology node

We describe the methodology and challenges in designing robust receiver and driver buffers in a state-of-the-art sub-100 nm CMOS technology. Issues addressed are the gate voltage limitations due to very thin gate oxides, channel hot carriers, process variability and design margins. The bi-directional buffer is 90 /spl mu/m/spl times/114 /spl mu/m in size and has a maximum speed of 150 MHz with a 50 ohm termination.