Karthik Yogendra

Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives

As CMOS technology begins to face significant scaling challenges, considerable research efforts are being directed to investigate alternative device technologies that can serve as a replacement for CMOS. Spintronic devices, which utilize the spin of electrons as the state variable for computation, have recently emerged as one of the leading candidates for post-CMOS technology. Recent experiments have shown that a nano-magnet can be switched by a spin-polarized current and this has led to a number of novel device proposals over the past few years. In this paper, we provide a review of different mechanisms that manipulate the state of a nano-magnet using current-induced spin-transfer torque and demonstrate how such mechanisms have been engineered to develop device structures for energy-efficient on-chip memory and logic.

Injection-Locked Spin Hall-Induced Coupled-Oscillators for Energy Efficient Associative Computing

In this paper, we show that the dynamics of injection-locked Spin Hall Effect Spin-Torque Oscillator (SHE-STO) cluster can be exploited as a robust primitive computational operator for non-Boolean associative computing. A cluster of SHE-STOs can be locked to a common frequency and phase with an injected ac current signal. DC input to each STO from external stimuli can conditionally unlock some of them. Based on the input dc signal, the degree of synchronization of SHE-STO cluster is detected by CMOS interface circuitry. The degree of synchronization can be used for associative computing/matching. We present a numerical simulation model of SHE-STO devices based on Landau-Lifshitz-Gilbert equation with spin-transfer torque term and Spin Hall Effect. The model is then used to analyze the frequency and phase locking properties of injection-locked SHE-STO cluster. Results show that associative computing based on the injection locked SHE-STO cluster can be energy efficient and relatively immune to device parameter variations and thermal noise.

Coupled Spin Torque Nano Oscillators for Low Power Neural Computation

We present coupled spin torque nano oscillators (STNOs) as electronic neurons for efficient brain-inspired computation. The coupled STNOs show two distinct outputs, depending on whether the frequencies are locked or not. The locking mechanisms are based on magnetic coupling or injection locking. The neuron firing threshold can be set by tuning the locking range of the coupled STNOs. We employ a crossbar array of programmable memory devices like memristors to implement electronic synapses that work seamlessly with the coupled STNOs for hardware implementation of neural networks. Results show that injection locking-based neuron model can be attractive from scaling point of view and computation like character recognition can be performed with energy consumption per neuron of ~1.8× and ~ 3× lower than the digital and the analog CMOS counterpart, respectively.

Design of ultra high density and low power computational blocks using nano-magnets

All Spin Logic (ASL) employs multiple nano-magnets interacting through spin-torque using metallic interconnect. ASL gates, being magneto-metallic, can operate at ultra low terminal voltage of few millivolts, and hence can be exploited for low power computation. Since, nano-magnets can preserve their state upon withdrawal of supply voltage, ASL can be pipelined for higher performance, without insertion of extra latches. However, pipelining requires the use of clocked CMOS transistors, which significantly increase the required supply voltage. In this work we analyse the design of an 8-bit, pipelined ASL multiplier, integrated with CMOS clocking circuitry. We propose a design scheme for 3-D ASL, which involves stacking of multiple ASL layers that are clocked using the same CMOS transistors. Stacking of N ASL layers using the proposed scheme can enhance the power saving as well as area density by factor of N. The proposed design scheme for magneto-metallic computational blocks can achieve more than two order of magnitude higher density and 10x lower power consumption as compared to 15nm CMOS design.

Design space exploration of FinFETs in sub-10nm technologies for energy-efficient near-threshold circuits

Near-threshold (near-VTH) operation of circuits by scaling the supply voltage (VDD) leads to maximum energy efficiency of the digital systems [1]. However, since the device characteristics are different in super-threshold (super-VTH) and near-VTH regions, devices optimized for standard VDD operation may be sub-optimal for low VDD operation [2]. Hence, there is a need to perform circuit-aware device design for near-VTH transistors. In this paper, we explore the design space of transistors in deeply scaled technologies (nominal gate length of 5nm) for nearVTH operation. We choose FinFETs for our study due to their excellent short channel characteristics. A detailed analysis of device circuit interactions is carried out using our simulation framework based on tight-binding bandstructure calculations, quantum ballistic models for devices and circuit simulations in HSPICE. We show the dependence of energy dissipation in near-VTH circuits on different device parameters. Based on our analysis, we discuss the design methodology for near-VTH devices.

Dual pillar spin torque nano-oscillator

We present a Dual Pillar Spin Torque Nano Oscillator (DP-STNO) suitable for energy efficient information processing. The proposed DP-STNO consists of a low resistance Giant Magneto-Resistance path that allows ultra-low voltage biasing of the oscillating ferromagnetic-free-layer, and a high resistance Tunneling Magneto-Resistance path that provides amplified RF-signal and facilitates easy sensing mechanism. The free-layers of multiple DP-STNOs can be coupled through dipolar-fields to accomplish complex signal processing tasks, like edge-extraction from an image, with high energy efficiency.

Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives

In this paper we discuss the potential of emerging spin-torque devices for computing applications. Recent proposals for spin-based computing schemes may be differentiated as all-spin? vs. hybrid, programmable vs. fixed, and, Boolean vs. non-Boolean. All-spin logic-styles may offer high area-density due to small form-factor of nano-magnetic devices. However, circuit and system-level design techniques need to be explored that leaverage the specific spin-device characterisitcs to achieve energy-efficiency, performance and reliability comparable to those of CMOS. The non-volatility of nano-magnets can be exploited in the design of energy and area-efficient programmable logic. In such logic-styles, spin-devices may play the dual-role of computing as well as memory-elements that provide field-programmability. Spin-based threshold logic design is presented as an example. Emerging spintronic phenomena may lead to ultra-low-voltage, current-mode, spin-torque switches that can offer attractive computing capabilities, beyond digital switches. Such devices may be suitable for non-Boolean data-processing applications which involve analog processing leading to highly energy-efficient information processing hardware for applicatons like pattern-matching, neuromorphic-computing, image-processing and data-conversion. Towards the end, we discuss the possibility of applying emerging spin-torque switches in the design of energy-efficient global interconnects, for future chip multiprocessors.

Exploring Spin-Transfer-Torque Devices for Logic Applications

As CMOS nears the end of the projected scaling roadmap, significant effort has been devoted to the search for new materials and devices that can realize memory and logic. Spintronics, which uses the spin of electrons to represent and manipulate information, is one of the promising directions for the post-CMOS era. While the potential of spintronic memories is relatively well known, realizing logic remains an open and critical challenge. All spin logic (ASL) is a recently proposed logic style that realizes Boolean logic using spin-transfer-torque devices based on the principle of nonlocal spin torque. ASL has advantages such as density, nonvolatility, and low operating voltage. However, it also suffers from drawbacks such as low speed and static power dissipation. Recent work has shown that, in the context of simple arithmetic circuits (adders and multipliers), the efficiency of ASL can be greatly improved using techniques that utilize its unique characteristics. An evaluation of ASL across a broad range of circuits, considering the known optimization techniques, is an important next step in determining its viability. In this paper, we propose a systematic methodology for the synthesis of ASL circuits. Our methodology performs various optimizations that benefit ASL, such as intracycle power gating, stacking of ASL nanomagnets, and fine-grained logic pipelining. We utilize the proposed methodology to evaluate the suitability of ASL implementations for a wide range of benchmarks, viz., random combinational and sequential logic, digital signal processing circuits, and the Leon SPARC3 general-purpose processor. Based on our evaluation, we identify: 1) the large current requirement of nanomagnets at fast switching speeds; 2) the static power dissipation in the all-metallic devices; and 3) the short spin flip length in interconnects as key bottlenecks that limit the competitiveness of ASL. We further evaluate the impact of various potential improvements in device parameters on the efficiency of ASL.

Domino-Style Spin–Orbit Torque-Based Spin Logic

We propose a new spin-orbit torque-based domino-style spin logic (SOT-DSL) that operates in a sequence of preset and evaluation modes of operation. During the preset mode, the output magnet is clocked to its hard axis using spin-Hall effect. In the evaluation mode, the clocked output magnet is switched by a spin current from the preceding stage. The nanomagnets in SOT-DSL are always driven by orthogonal spins rather than collinear spins, which in turn eliminates the incubation delay and allows fast magnetization switching. Based on our simulation results, SOT-DSL shows up to 50% improvement in energy consumption compared to all-spin logic. Moreover, SOT-DSL relaxes the requirement for buffer insertion between long spin channels and significantly lowers the design complexity.

Energy efficient computing using coupled Dual-Pillar Spin Torque Nano Oscillators

We present a Dual-Pillar Spin-Torque Nano Oscillator (DP-SNTO) suitable for energy-efficient information processing. The proposed DP-STNO consists of a low resistance Giant Magneto-Resistance (GMR) path that allows ultra-low voltage biasing of the oscillating ferromagnetic-free-layer, and a high resistance Tunneling Magneto-Resistance (TMR) path that provides amplified RF-signal and facilitates easy sensing mechanism. The free-layers of multiple DP-STNOs can be coupled using spin-wave (or electrical coupling) to accomplish complex signal processing tasks, like image-segmentation, with high energy-efficiency. Simulations show that DP-STNO can be ~50× more energy-efficient as compared to a standard two-terminal STNO and can hence be more suitable for integration with CMOS for non-Boolean computing and RF-signaling applications.