Kasin Vichienchom

Modified Graph-Based Detection Methods for Two-Dimensional Interference Channels

Two-dimensional (2-D) interference channels with inter-symbol interference (ISI) and inter-track interference (ITI) exist in the magnetic recording systems at high areal density. A number of 2-D detection methods have recently been proposed for the multi-track processing of the 2-D channels. Graph-based detector with the belief propagation algorithm appears as an alternative method, but at a degraded performance and high complexity level. In this work, we propose two methods to modify the graph-based (GB) detector. One applies a serial scheduling to the GB detector, while the other modifies the GB detection by ignoring some connections during one direction of the reliability updates in the factor graph leading to the reduction of short cycles. The simulation results show that the proposed GB detectors give better bit error rate performances than the other GB detectors.

Performance of Log-MAP algorithm for graph-based detections on the 2-D interference channel

The read channel of magnetic recording system is affected by two-dimensional interference channel that is a combination of inter-symbol interference and inter-track interference. Inter-track interference is one of the biggest challenges in the high density magnetic recording systems and it can degrade the performance of the channels. In this work, we compare three variations of log-MAP algorithms for graph-based detectors in two-dimensional interference channels. The simulation results show the performance of the graph-based detector with the full log-MAP and extended log-MAP algorithms achieve the gains of about 0.1 and 0.05 dB at BER = 10-5, over the max approximation on bit patterned media recording system with the areal density 2.5 Tbits/in2.

Study the Effect of Stripe Height and Read Track Width on Blocking Temperature

The magnetic read head technology is continuously designed to become smaller in order to get the highest areal density. Due to small volume the thermal stability is investigate for this study. The objective of this research is to study the relationship between the dimension of read head sensor and its blocking temperature. Stripe Height and Read track width were considered for this study. The result is blocking temperature decreasing with short stripe height. Advantage of this study is the reliability issue especially blocking temperature was captured by using resistance.

Free Layer Characterization of TMR Head with Multi-Stripe Height by Using Ferro Magnetic Resonance Analyzer (FMRA)

As continued reducing the track width (TW) of magnetic read sensor for gaining areal density in hard disk drive (HDD) industry, stripe height (SH) is needed to be reduced as keeping aspect ratio(TW/SH) for maintain resistance and signal constant. This paper is proposed to characterize the free layer behavior of tunneling magneto resistive (TMR) head with multiple SH by using ferro magnetic resonance analyzer (FMRA) that is able to analyze by layer-level state without applying external field. The results are found that, at shorter SH, effective stiffness field of free layer is increased which is based on decreasing FMR amplitude and increasing FMR frequency. As a result, magnetic read sensor is shown less sensitivity and signal to noise ratio (SNR) with shorter SH. The SH is a correlated function of the effective stiffness field in free layer that is referred to changed shape anisotropy field which has an effect to read ability.

Improved 2-D Graph-Based Detectors for 2-D Interference Channels

The 2-D interference channels, which consist of intersymbol interference as well as intertrack interference (ITI), appear in high-density recording channels. A graph-based detector has received much attention since it is a real 2-D detector, which can recover data from multiple tracks or each 2-D page simultaneously. In this paper, we propose two approaches to improve the performances of graph-based detectors. For the first method (M1), which processes data on a 2-D page, the system equalizes 2-D interference channel into two 1-D targets, horizontal and vertical directions followed by two corresponding graph detectors. The second method (M2) is similar to the first one, but the 2-D channel is equalized into two 2-D targets with and without cornered ITIs, respectively, in order to better handle the effects of cornered ITIs. Compared with the full-graph detector, the method M1 offers reduced-complexity due the fewer number of edges from the factor nodes. The simulation results on the 3 × 3 channel matrix with 2% cornered ITI show that the proposed methods achieve the gains of about 1.0 and 1.7 dB, respectively, at the BER of 10-5 over the full graph detector. As the cornered ITI levels increase, the method M2 gives the larger gains over the others. When the media noise is accounted for, the method M2 still gives the best performances. Finally, the mutual information of the three graph detectors for the 2-D channels is computed and compared.

A 0.5 volt rail-to-rail CMOS pseudo-differential OTA using simple feed-forward technique

This paper presents a low voltage CMOS pseudo differential OTA using simple feed-forward technique. The circuit employs feed-forward technique to suppress the common-mode gain, and positive feedback to enhance the output impedance. The circuit is designed using 0.18 µm CMOS technology under 0.5 V supply. The simulation results show rail-to-rail input/output swing, achieved with low common-mode gain (−35 dB). The output swing of the circuit is 0.3 Vpp. The power dissipation of the circuit is 50 µW.

A 1 GHz CMOS analog equalizer for perpendicular magnetic recording

This paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching error in analog samples due to rotating switch matrix. A 7-tap filter circuit based on GPR2 target was designed and simulated using TSMC 0.18 µm CMOS process parameters. Simulation results show good agreement with the results of the system level simulation. At 1 GHz sampling frequency the equalizer dissipates 1.5 mW.