Katja Puschkarsky

Circuit relevant HCS lifetime assessments at single transistors with emulated variable loads

Hot carrier induced degradation of MOSFETs is still a concern for circuit reliability and not yet fully understood [1-4]. On the one hand stress measurements at single devices reveal critical parameter degradation for modern technologies especially at high VD=VG. On the other hand there are several publications stating that at least for combinational logic HCS plays only minor role for lifetime limits [e.g. 5]. In 2010 we have published experimental data of an integrated aging monitor demonstrating the small HCS impact on the lifetime of a critical logic path [6]. This discrepancy needs further investigation. An accurate circuit relevant assessment method is required to evaluate the correct HCS impact on lifetime. In this paper we introduce a new methodology to investigate and qualify product relevant HCS lifetime at single test devices with waveform AC-stress. We investigate the proportion of occurring device degradation mechanisms during digital circuit operations and clarify the different impact factors. Finally we compare the results of the new set-up in detail with the standard worst case approach based on experimental data in 130nm and 40nm technology nodes.

NBTI: Experimental investigation, physical modelling, circuit aging simulations and verification

Abstract For more than 10xa0years a major part of MOSFET reliability publications are dealing with (N)BTI. The degradation and recovery mechanism is still not fully understood (Grasser, 2014). New publications demonstrate incessantly the agile debate on this important transistor aging phenomenon. In this paper we want to illuminate four important subareas for the understanding of NBTI. First, we will discuss experimental investigations. Depending on the pursued goal of the measurements different set-ups are required to gain the desired information. To get meaningful statements regarding the median NBTI degradation of MOSFET with a relatively small number of test devices, e.g. for regular lifetime predictions, DUTs with larger active area are used. The relatively high number of defects within one transistor delivers stable (averaged) parameter shifts with a small number of DUTs. Relatively small area devices are the best choice to investigate the physical nature of the degradation and recovery mechanisms. The small number of defects within those devices enables to obtain and investigate the trapping and de-trapping of single charges. To investigate the NBTI impact on the parameter variability array structures with a higher number of devices under test (DUTs) are appropriate. The very fast and strong recovery behavior of NBTI has to be considered for the test structure design and for the measurement set-up. Based on the measurement results and gained knowledge we can refine the modelling of the degradation and recovery mechanism. We could improve the understanding of the temperature dependence and utilize this knowledge to reduce measurement efforts for model calibration for a circuit aging simulator (Pobegen and Grasser, 2013). An adequately accurate model at a manageable effort for characterization and implementation is a key factor for a successful integration of an aging simulator in the design flow. A correct modelling of the parameter recovery during circuit function is especially challenging. The last chapter introduces a new method to verify the NBTI model and the correct implementation into a circuit aging simulator with real hardware measurements. An arbitrary waveform generator is used to drive single transistors in identical operation modes with identical sequence and proportion of each single operating point as during real circuit operation. In this manner, the calculated drift for one transistor in a circuit can be compared with a measurement drift for a given stress pattern.

The impact of mixed negative bias temperature instability and hot carrier stress on single oxide defects

Even though transistors are rarely subjected to idealized bias temperature instability or hot carrier stress conditions in circuits, there is only a limited number of studies available on mixed bias temperature instability and hot carrier stress. Here we summarize the results of the first study of mixed negative bias temperature instability and hot carrier stress (drain stress voltage |VstrD|> 0 V and gate stress voltage |VstrD| ≥ |VDD|) at the single oxide defect level in nano-scale SiON pMOSFETs. We found that less defects contribute to a threshold voltage shift ΔVth during recovery and thus to the recoverable degradation than would be expected from a simple electrostatic model. Time-dependent defect spectroscopy measurements show that even defects at the source side of the oxide can remain neutral after mixed negative bias temperature instability and hot carrier stress although they are fully charged after homogeneous negative bias temperature instability stress. As a consequence, they do not contribute to a ΔVth drift after mixed negative bias temperature instability and hot carrier stress. We show that this unexpected reduction in the defects occupancy can be consistently explained by non-equilibrium processes induced by the large drain voltage such as impact ionization.