Hans Reisinger

A novel capacitor technology based on porous silicon

A capacitor based on an electrochemically etched macroporous silicon substrate and a layered dielectric (ONO) is presented. This solid-state technology allows us to realize values of specific capacitance which so far could only be reached by electrolytic capacitors. The dependence of the capacitance on temperature, frequency, applied bias and time of operation is found to be negligible. Due to a low series resistance and a operating temperature of at least 200 °C the device withstands high a.c. currents. Being a silicon chip, the capacitor is fully compatible with todays surface mounted device and multi-chip module technologies.

Dielectric breakdown, reliability and defect density of (Ba/sub 0.7/Sr/sub 0.3/)TiO/sub 3/ (BST)

Summary form only given. A thorough electrical characterization of BST with focus on lifetime, large device relevant areas (2/sub c/m/sup 2/) and defect density was carried out. As a result we think that BST with an SiO/sub 2/ equivalent thickness t/sub oxeq/ of 5 /spl Aring/ is able to meet the requirements of Gb DRAMs with /spl plusmn/1 V operating voltage.