Ramchan Woo

A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

A 36 mm/sup 2/ graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor,a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD)vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-/spl mu/m 6-metal standard CMOS logic process.

A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications

A 121 mm/sup 2/ graphics LSI is for portable 2D/3D graphics and MPEG4 applications. The LSI contains a RISC processor with MAC, a 3D rendering engine, 29Mb DRAM and is built in a 0.16/spl mu/m pure DRAM technology. Programmable clocking allows the LSI to operate in several power modes for various applications. In lower cost mode, power consumption is under 210mW, delivering 264M texture mapped pixels per second.

An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications

An 84 mm/sup 2/ 160 mW programmable processor in 0.18 /spl mu/m EMC technology consists of 32 b RISC with MAC, 20 MHz motion compensation accelerator for MPEG-4 at SP, 3D rendering engine with 2.2 M polygon/s at 20 MHz, and 7.125 Mb embedded DRAM with single bitline writing scheme.

A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications

The real time 3D graphics becomes one of the attractive applications for 3G wireless terminals although their battery lifetime and memory bandwidth limit the system resources for graphics processing. Instead of using the dedicated hardware engine with complex functions, we propose an efficient hardware architecture of low power vertex shader with programmability. Our architecture includes the following three features: I) a fixed-point SIMD datapath to exploit parallelism in vertex processing while keeping the power consumption low, II) a multithreaded coprocessor interface to decrease unwanted stalls between the main processor and the vertex shader, reducing power consumption by instruction-level power management, III) a programmable vertex engine to increases the datapath throughput by concurrent operations with main processor. Simulation results show that full 3D geometry pipeline can be performed at 7.2M vertices/sec with 115mW power consumption for polygons using the OpenGL lighting model. The improvement is about 10 times greater than that of the latest graphics core with floating-point datapath for wireless applications in terms of processing speed normalized by power consumption, Kvertices/sec per milliwatt.

Low-power 3D graphics processors for mobile terminals

A full 3D graphics pipeline is investigated, and optimizations of graphics architecture are assessed for satisfying the performance requirements and overcoming the limited system resources found in mobile terminals. Two mobile 3D graphics processor architectures, RAMP and DigiAcc, are proposed based on the analysis, and a prototype development platform (REMY) is implemented. REMY includes a software graphics library and simulation environment developed for more flexible realization of mobile 3D graphics. The experimental results demonstrate the feasibility of mobile 3D graphics with 3.6 Mpolygons/s at 155 mW power consumption for full 3D operation.

A 670 ps, 64 bit dynamic low-power adder design

A 64 bit dynamic low-power adder has been designed and fabricated for 2.5 V 0.25-/spl mu/m 1-poly 5-metal CMOS technology. Fast carry propagation is obtained by fast P generation, parallel quaternary-tree form of group carry (GC) selection and conditional sum selection. The results of proposed adder architecture show that propagation delay, power consumption, and the area are 670 ps, 100 mW, and 0.16 mm/sup 2/, respectively.

A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth

Recently, the level of realism in PC graphics applications has been approaching that of high-end graphics workstations, necessitating a more sophisticated texture data cache memory to overcome the finite bandwidth of the AGP or PCI bus. This paper proposes a multilevel parallel texture cache memory to reduce the required data bandwidth on the AGP or PCI bus and to accelerate the operations of parallel graphics pipelines in PC graphics cards. The proposed cache memory is fabricated by 0.16-/spl mu/m DRAM-based SOC technology. It is composed of four components: an 8-MB DRAM L2 cache, 8-way parallel SRAM L1 caches, pipelined texture data filters, and a serial-to-parallel loader. For high-speed parallel L1 cache data replacement, the internal bus bandwidth has been maximized up to 75 GB/s with a newly proposed hidden double data transfer scheme. In addition, the cache memory has a reconfigurable architecture in its line size for optimal caching performance in various graphics applications from three-dimensional (3-D) games to high-quality 3-D movies.

A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals

A low-power three-dimensional (3-D) rendering engine with two texture units and 29-Mb embedded DRAM is designed and integrated into an LSI for mobile third-generation (3G) multimedia terminals. Bilinear MIPMAP texture-mapped 3-D graphics can be realized with the help of low-power pipeline structure, optimization of datapath, extensive clock gating, texture address alignment, and the distributed activation of embedded DRAM. The scalable performance reaches up to 100 Mpixels/s and 400 Mtexels/s at 50 MHz. The chip is implemented with 0.16-/spl mu/m pure DRAM process to reduce the fabrication cost of the embedded-DRAM chip. The logic with DRAM takes 46 mm/sup 2/ and consumes 140 mW at 33-MHz operation, respectively. The 3-D graphics images are successfully demonstrated by using the fabricated chip on the prototype PDA board.

Optimization of portable system architecture for real-time 3D graphics

The optimal architecture of personal digital assistants (PDA) system for real-time 3D graphics was analyzed by simulating the 3D applications on the various Advanced RISC Machines (ARM) processor platforms. Simulation results show that for 256/spl times/256 screen resolution, even the performance of 200 MHz StrongARM with 160 MHz floating point unit (FPU) shows only 1.78 % of the requirement of full 3D pipeline. To realize the real-time 3D graphics on PDA, the optimal architecture must contain hardware acceleration engine with embedded DRAM as the rendering stage. In this architecture, MAC-enhanced ARM9 without FPU that is used as a host processor can provide the necessary geometry operations and we verified this architecture by the implementation of a PDA chip.

A fixed-point multimedia coprocessor with 50Mvertices/s programmable SIMD vertex shader for mobile applications

A fixed-point multimedia coprocessor is designed and integrated into an ARM-10 based mobile graphics processor for portable 2D and 3D multimedia applications. The user-programmable SIMD vertex shader with ARM-10 co-processor architecture realizes advanced 3D graphics algorithms and various multimedia functions. Different from conventional ARM coprocessor architecture, the multimedia coprocessor implements dual operations, by which parallel and streaming multimedia processing is enabled in mobile applications. For low power consumption, fixed-point SIMD datapath is designed with instruction-wise clock gating. The co-processor takes 10.2mm/sup 2/ in 0.18/spl mu/m 6-metal standard CMOS logic process and achieves 50Mvertices/s graphics performance with 75.4mW power consumption.