Katsuhiko Kubota

Water-related threshold voltage instability of polysilicon TFTs

Negative bias-temperature (NBT) instability of polysilicon thin film transistors (TFTs) has been studied. We found water is strongly related to this phenomenon and can result in a threshold voltage shift of 1 V or more within a short time under NBT stress. This paper shows the results supporting this fact and proves, by using thin LPCVD SiN films, the suppression of water penetration and/or content in the oxides is essential in reducing this instability to an acceptable level. A qualitative model is presented to explain the role of water and experimental results.<<ETX>>

Degradation of I/O devices due to ESD-induced dislocations

Degradation in leakage current characteristics of I/O circuits due to ESD events has been studied. TEM observations revealed the generation of crystalline defects in the silicon substrate such as dislocations induced by ESD stress which increased the reverse leakage current level of the p-n junctions in the I/O circuits. We found that current crowding occurs in the silicon surface region during an ESD event resulting in defect generation. We also show that optimal impurity profiles for protection devices can avoid such current crowding and hence the leakage current degradation.<<ETX>>

Detailed observation of small leak current in flash memories with thin tunnel oxides

This paper describes a method for measuring the small current through the oxides on the order of 10/sup -20/ A or less using a floating gate MOSFET and the application results on flash memories with thin tunnel oxides. The method is based on accurate measurement of the threshold voltage of a floating gate MOSFET with no charge in the floating gate. We applied the method to flash memories to investigate the leakage current behaviour through thin tunnel oxides with very small areas (<0.16 /spl mu/m/sup 2/), and found some anomalous phenomena which cannot be obtained from stress-induced leakage current (SILC) measurements using large capacitors. We also discuss possible mechanisms to explain the phenomena.

Anomalous Leakage Current Model for Retention Failure in Flash Memories

l. Introduction Oxide reliability is always one of the most crucial issues in flash memories. Although SILC (Stress-Induced Leakage Current) is now widely recognized, a retention lifetime of a megabit-scale memory is determined by a very small number of failure bits showing an anomalously large SILC tl-31. However no models for the retention lifetime of failure bits have been established yet. In this paper, for the first time, we develop a quantitative model for this anomalous SILC arid investigate the properties of retention lifetime of failure bits.

Effects of process-induced mechanical stress on ESD performance

We studied the generation of dislocations during an ESD event by electrothermal and mechanical stress simulations based on analysis of critical mechanical stress for defect formation. We found the local thermal stress by ESD generates dislocations cooperatively with the residual mechanical stress in the Si substrate due to field oxidation. This means that process-induced mechanical stress is another key factor for controlling ESD performance, which will be important especially in low-power applications with severe leak requirements.

A practical method for extracting impurity profiles and effective mobilities of MOSFET's with nonuniform channel doping

Complete profiling of channel impurity concentration up to the surface is presented using Gaussians whose parameters are determined, giving optimum fits to the measured capacitance voltage (C-V) profiles. A rectangular capacitor with a large aspect ratio is found to be effective in reducing series resistance for accurate (C-V) measurements at high frequencies. Effective mobilities are extracted from practical MOSFETs based on numerical analysis of the field effects using the obtained profiles and compared to those for uniform doping.<<ETX>>

AC hot-carrier degradation in the super-100 MHz operation range

Recent progress in operation speed of VLSIs requires accurate prediction of AC circuit lifetimes determined by hot carrier degradation in the frequency range over 100 MHz. Our main concerns are the validity of quasi-static calculations for AC lifetimes and the effects of enhanced degradation in highspeed operation. Since few reports have referred to measured results in the super-100MHz frequency range, we studied AC hot-carrier degradation up to 369 MHz using high-speed ring oscillators. Oscillation waveforms were detected with an electron-beam tester since inaccurate waveforms by simulation based on erroneous estimates for stray capacitance may lead to incorrect circuit lifetimes in quasi-static calculation.<<ETX>>

Dielectric Degradation Mechanism of SiO2 Examined by First-Principles Calculations. Electronic Conduction Associated with Electron Trap Levels in SiO2 and Stability of Oxygen Vacancies Under an Electric Field.

We studied the degradation mechanism of silicon dioxide under an electric field using first-principles calculations. First, we determined that the distance between oxygen vacancies primarily plays the role of electronic interaction of electron trap levels and that a critical distance of 12 A, exists. At this critical distance, the leakage conduction mechanism is varied from insulator (hopping) to metallic. Second, we examined the stability of oxygen vacancies under an applied field. We determined that the oxygen vacancy pair within 7 A is more stable than the one which is further apart when it becomes positively charged under a high field.

Quantitative analysis of SILCs (Stress Induced Leakage Currents) based on the inelastic trap-assisted tunneling model

We have successfully developed a new quantitative analytical ITAT-based SILC model which can explain both of the two field dependencies, i.e. Fowler-Nordheim (FN)-field and the direct tunneling (DT)-field dependent of A-mode and B-mode SILCs. While DT-field dependence of A-mode comes from the single trap assisted tunneling, FN-field dependence of B- mode originates at the tunneling via the multi-trap leakage path. We have also developed an analytical model for the anomalous SILC of the flash memory cell and investigate the properties of retention lifetime of failure bits. The anomalous SILC shows the DT-field dependence because of the tunneling via the incomplete multi-trap path. A remarkable behavior of retention characteristics predicted by our models is a nearly logarithmic time dependence. The Fowler- Nordheim tunneling model leads to an overestimation of lifetime at low Vth region. To take into account a position of each trap and clarify the detail characteristics of SILC, we have proposed a new Monte Carlo like approach for hopping conduction and successfully explained the anomalous SILC using only physical based parameters.

An in-process monitoring method for electromigration resistance of multilayered metal interconnects

This paper describes it method for monitoring electromigration (EM) resistance of multilayered metal interconnects which have been widely used in recent LSI technologies. We studied the combination of SWEAT (Standard Wafer-Level Electromigration Acceleration Test) patterns and the BEM (Breakdown Energy of Metal) method. We found that SWEAT pattern has a threshold length in its narrow portion to grow voids induced by EM, and optimized the conditions for the BEM method in terms of temperature and ramping rate. We have realized an in-process EM monitoring method which takes 4 minutes per sample at room temperature using the above combination.