Kazuhiro Komori

A flash-erase EEPROM cell with an asymmetric source and drain structure

A flash-erase EEPROM cell which consists of a single floating gate transistor is described. The cell is based on self-aligned double polysilicon stacked gate structure without a select transistor. It is programmed and erased by hot electrons at the drain edge similar to a UV-EPROM, and by Fowler-Nordheim tunneling of electrons from the floating gate to the source, respectively. An asymmetry in source and drain regions is introduced to enable fast program/erase operation. In addition, an n+concentration in the source region is optimized to achieve reproducible erasure, which is indispensable to avoid over-erasing problem. The optimized cell enables an erasing time of less than one millisecond with 12. 5 V on the source, and a scatter of erased Vth is almost negligible. Endurance and data retention characteristics is also adequate for implementation in memory chips. The small cell area of 9.3µm2is accomplished in a 0.8µm technology.

Two dimensionally inhomogeneous structure at gate electrode/gate insulator interface causing Fowler-Nordheim current deviation in nonvolatile memory

The gate electrode polycrystalline silicon (gate poly-Si)/gate insulator SiO/sub 2/ interface structure has been studied for obtaining reliable nonvolatile memory devices. The voltage deviation of Fowler-Nordheim tunneling current of the devices is discussed in terms of the SiO/sub 2/ surface roughness. High resolution scanning electron microscope (SEM) and atomic force microscope (AFM) measurements indicate that two dimensional nanometric oxide ridges are formed at the interface. It was found that a phosphorus dose below 2*10/sup 15/ cm/sup -2/, an annealing temperature below 900 degrees C, and the use of arsenic as a dopant resulted in the smooth SiO/sub 2/ surfaces. The reduction in the voltage deviation of the tunneling current is correspondingly obtained under these conditions. The oxide ridge growth can be explained by excess phosphorus distribution at grain boundaries and phosphorus-rich SiO/sub 2/ formation.<<ETX>>

A high performance memory cell technology for mega bit EPROMS

A high performance memory cell technology for mega bit EPROMs has been developed using 1.3 µm process. Deeply Doped Channel ( DDC ) and Double Step Drain ( DSD ) structures incorporated into the scaled memory cell improve programming speeds by more than one order of magnitude with maintaining high breakdown voltages, small parasitic effects,and soft-write immunity. This technology has been successfully applied to one mega bit CMOS EPROMs with a cell size of 19.27 µm2and realized programming time less than 10 µs for a programming voltage of 12.5 V.